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january 2013 i ? 2013 microsemi corporation proasic3l low power flash fpgas with flash*freeze technology features and benefits low power ? dramatic reduction in dynamic and static power savings ? 1.2 v to 1.5 v core and i/o voltage support for low power ? low power consumption in flash*freeze mode allows for instantaneous entry to / exit from low-power flash*freeze mode ? supports single-voltage system operation ? low-impedance switches high capacity ? 250,000 to 3,000,000 system gates ? up to 504 kbits of true dual-port sram ? up to 620 user i/os reprogrammable flash technology ? 130-nm, 7-layer metal (6 copper), flash-based cmos process ? instant on level 0 support ? single-chip solution ? retains programmed design when powered off high performance ? 350 mhz (1.5 v systems) and 250 mhz (1.2 v systems) system performance ? 3.3 v, 66 mhz, 66-bit pci (1.5 v systems) and 66 mhz, 32-bit pci (1.2 v systems) in-system programming (isp) and security ? isp using on-chip 128-bit advanced encryption standard (aes) decryption via jt ag (ieee 1532?compliant) ? flashlock ? to secure fpga contents high-performance r outing hierarchy ? segmented, hierarchical routing and clock structure ? high-performance, low-skew global network ? architecture supports ultra-high utilization advanced and pro (professional) i/os ? 700 mbps ddr, lvds-capable i/os ? 1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages?up to 8 banks per chip ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v / 1.8 v / 1.5 v / 1.2 v, 3.3 v pci / 3.3 v pci-x, and lvcmos 2.5 v / 5.0 v input ? differential i/o standards: lvpecl, lvds, b-lvds, and m-lvds ? voltage-referenced i/o standards: gtl+ 2.5 v / 3.3 v, gtl 2.5 v / 3.3 v, hstl class i and ii, sstl2 class i and ii, sstl3 class i and ii (a3pe3000l only) ? wide range power supply voltage support per jesd8-b, allowing i/os to operate from 2.7 v to 3.6 v ? wide range power supply voltage support per jesd8-12, allowing i/os to operate from 1.14 v to 1.575 v ? i/o registers on input, output, and enable paths ? hot-swappable and cold-sparing i/os programmable output slew rate and drive strength ? programmable input delay (a3pe3000l only) ? schmitt trigger option on single-ended inputs (a3pe3000l) ? weak pull-up/-down ? ieee 1149.1 (jtag) boundary scan test ? pin-compatible packages across the proasic ? 3l family (except pq208) clock conditioning circuit (ccc) and pll ? six ccc blocks, one with integrated pll (proasic3l) and all with integrated pll (proasic3el) ? configurable phase shift, multiply/divide, delay capabilities, and external feedback ? wide input frequency range 1.5 mhz to 250 mhz (1.2 v systems) and 350 mhz (1.5 v systems)) srams and fifos ? variable-aspect-ratio 4,608-bit ram blocks (1, 2, 4, 9, and 18 organizations available) ? true dual-port sram (except 18) ? 24 sram and fifo configurations with synchronous operation: ? 250 mhz: for 1.2 v systems ? 350 mhz: for 1.5 v systems arm ? processor support in proasic3l fpgas ? arm cortex?-m1 soft processor available with or without debug table 1 ? proasic3 lo w-power product family proasic3l devices a3p250l a3p600l a3p1000l a3pe3000l arm cortex-m1 devices 1 m1a3p600l m1a3p1000l m1a3pe3000l system gates 250,000 600,000 1,000,000 3,000,000 versatiles (d-flip-flops) 6,144 13,824 24,576 75,264 ram kbits (1,024 bits) 36 108 144 504 4,608-bit blocks 82432112 flashrom kbits 1111 secure (aes) isp 2 yes yes yes yes integrated pll in cccs 3 1116 versanet globals 18 18 18 18 i/o banks 4448 maximum user i/os 157 235 300 620 package pins vqfp pqfp fbga vq100 pq208 fg144, fg256 pq208 fg144, fg256, fg484 pq208 fg144, fg256, fg484 pq208 3 FG324, fg484, fg896 notes: 1. refer to the cortex-m1 product brief for more information. 2. aes is not available for arm cortex-m1 proasic3l devices. 3. for the a3pe3000l, the pq208 pa ckage has six cccs and two plls. revision 13
proasic3l low power flash fpgas ii revision 13 i/os per package 1 proasic3l low-power devices a3p250l 2 a3p600l a3p1000l a3pe3000l arm cortex-m1 devices m1a3p600l m1a3p1000l m1a3pe3000l 3 package i/o type single- ended i/o 4 differential i/o pairs single- ended i/o 4 differential i/o pairs single- ended i/o 4 differential i/o pairs single- ended i/o 4 differential i/o pairs vq1006813 ????? pq208 151 34 154 35 154 35 147 65 fg144 972497259725 fg256 157 38 177 43 177 44 ? ? FG324 ? ? ? ? ? ? 221 110 fg484 ? ? 235 60 300 74 341 168 fg896 ? ? ? ? ? ? 620 310 notes: 1. when considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements. 2. for a3p250l devices, the maximum number of lvpecl pairs in east and west banks cannot exceed 15. 3. arm cortex-m1 support is tbd on this device. 4. each used differential i/o pair reduces the number of single-ended i/os available by two. 5. fg256 and fg484 are footprint-compatible packages. 6. "g" indicates rohs-compliant packages. refer to "proasic3l ordering information" on page iii for the location of the "g" in the part number. 7. for a3pe3000l devices, the usage of certain i/o standards is limited as follows: ? sstl3(i) and (ii): up to 40 i/os per north or south bank ? lvpecl / gtl+ 3.3 v / gtl 3.3 v: up to 48 i/os per north or south bank ? sstl2(i) and (ii) / gtl+ 2.5 v/ gtl 2. 5 v: up to 72 i/os per north or south bank 8. when the flash*freeze pin is used to directly enable flash*freez e mode and not as a regular i/o, the number of single-ended u ser i/os available is reduced by one. table 2 ? proasic3l fpgas package sizes dimensions package vq100 pq208 fg144 fg256 FG324 fg484 fg896 length width (mm\mm) 14 14 28 28 13 13 17 17 19 19 23 23 31 31 nominal area (mm 2 ) 196 784 169 289 361 529 961 pitch (mm) 0.5 0.5 1.0 1.0 1.0 1.0 1.0 height (mm) 1.00 3.40 1. 45 1.60 1.63 2.23 2.23
proasic3l low power flash fpgas revision 13 iii proasic3l ordering information speed grade blank = standard 1 = 15% faster than standard a3p1000l fg _ part number proasic3l devices 1 package type vq = very thin quad flat pack (0.5 mm pitch) 144 i y package lead count g lead-free packaging application (temperature range) blank = commercial (0c to +70c ambient temperature) i = industrial ( ? 40c to +85c ambient temperature) blank = standard packaging g= rohs-compliant (green) packaging 250,000 system gates a3p250l = 600,000 system gates a3p600l = 1,000,000 system gates a3p1000l = 3,000,000 system gates a3pe3000l = proasic3l devices with cortex-m1 600,000 system gates m1a3p600l = 1,000,000 system gates m1a3p1000l = 3,000,000 system gates m1a3pe3000l = pq = plastic quad flat pack (0.5 mm pitch) fg = fine pitch ball grid array (1.0 mm pitch) security feature y = device includes license to implement ip based on the cryptography research, inc. (cri) patent portfolio blank = device does not include license to implement ip based on the cryptography research, inc. (cri) patent portfolio
proasic3l low power flash fpgas iv revision 13 temperature grade offerings speed grade and temperature grade matrix proasic3l device status contact your local microsemi soc products gr oup representative for device availability: http://www.microsemi.com/soc/contact/default.aspx . package a3p250l a3p600l a3p1000l a3pe3000l arm cortex-m1 devices m1a3p600l m1a3p1000l m1a3pe3000l vq100 c, i ? ? pq208 c, ic, ic, ic, i fg144 c, ic, ic, i fg256 c, ic, ic, i FG324 ? ? ? c, i fg484 ? c, ic, ic, i fg896 ? ? ? c, i notes: 1. c = commercial temperature range: 0c to 70c ambient temperature. 2. i = industrial temperature range: ?40c to 85c ambient temperature. temperature grade std. ?1 c 1 33 i 2 33 notes: 1. c = commercial temperature range: 0c to 70c ambient temperature. 2. i = industrial temperature range: ?40c to 85c ambient temperature. proasic3l devices status m1 proasic3l devices status a3p250l production a3p600l production m1a3p600l production a3p1000l production m1a3p1000l production a3p3000l production m1a3p3000l production
proasic3l low power flash fpgas revision 13 v table of contents proasic3l device family overview general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 proasic3l dc and swit ching characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 user i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 versatile characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121 global resource characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-127 clock conditioning circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132 embedded sram and fifo characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-134 embedded flashrom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-148 jtag 1532 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-149 pin descriptions and packaging supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 user pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 special function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 package pin assignments vq100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 pq208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 fg144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 fg256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 FG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 fg484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 fg896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

revision 13 1-1 1 ? proasic3l device family overview general description the proasic3l family of microsem i flash fpgas dramatically reduc es dynamic power consumption by 40% and static power by 50% compared to the equivalent proasic3 device. these power savings are coupled with performance, density, true single-chip , 1.2 v to 1.5 v core and i/o operation as low as 1.2 v, reprogrammability, and advanced features. using microsemi's proven flash*freeze technolog y enables users to shut off dynamic power instantaneously and switch the device to static mode without the need to switch off clocks or power supplies while retaining internal states of the de vice. this greatly simplifies power management on a board done through i/os and clocks. in addition, optimized soft ware tools using power-driven layout provide instant push-bu tton power reduction. nonvolatile flash technology gives proasic3l de vices the advantage of being a secure, low-power, single-chip solution that is instant on. proasic3 l offers dramatic dynamic power savings giving the fpga users flexibility to combine low power with high performance. these features e nable designers to create high -density systems using existing asic or fpga design flows and tools. proasic3l devices offer 1 kbit of on-chip, reprogra mmable, nonvolatile flashrom storage as well as clock conditioning circuitry (ccc) based on an integr ated phase-locked loop (pll). proasic3l devices support devices from 250 k system gates to 3 m illion system gates wi th up to 504 kbits of true dual-port sram and 620 user i/os. m1 proasic3l devices support the high-performance, 32-bit cortex-m1 processor developed by arm for implementation in fpgas. arm cortex-m1 is a so ft processor that is fu lly implemented in the fpga fabric. it has a three-stage pipeline that offers a good balance between low-power consumption and speed when implemented in an m1 proasic3l device . the processor runs the armv6-m instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. arm cortex-m1 is available for free from microsemi for use in m1 proasic3l fpgas. the arm-enabled devices have microsemi soc produc ts group ordering numbers that begin with m1 and do not support aes decryption. flash*freeze technology the proasic3l devices offer microsemi's proven flash*freeze technology, which allows instantaneous switching from an active state to a static state. proasic3l devices do not need additional components to turn off i/os or clocks while retaining the design in formation, sram content, and registers. flash*freeze technology is combined wi th in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. the ability of proasic3l devices to support a wide range core voltage (1.2 v to 1.5 v) allows for an even greater reduction in power consumption, wh ich enables low total system power. when the proasic3l device enters flash*freeze mode , the device automatically shuts off the clocks and inputs to the fpga core; when the device exits flash*freeze mode, all activity resumes and data is retained. the availability of low-power modes, combined wit h a reprogrammable, single-chip, single-voltage solution, make proasic3l devices suitable for low-power data transfer and manipulation in portable media, secure communications, radio applications as well as high performance portable, industrial, test, scientific, and medical applications.
proasic3l device family overview 1-2 revision 13 flash advantages low power the proasic3l family of microsemi flash-bas ed fpgas provide a low-power advantage, and when coupled with high performance, enables designers to make power-smart choices using a single-chip, reprogrammable, and instant on device. proasic3l devices offer 40% dynamic power and 50% static power savings compared to the equivalent proasic3 device by reducing the core operating volt age to 1.2 v. in addition, the power driven layout (pdl) feature in libero ? system-on-chip (soc) offers up to 30% additional power reduction over the standard timing-driven place-and-route (tdpr). with flash*freeze technology, proasic3l devices are able to retain device sram and logic while dynamic power is reduced to a minimum, without the need to stop clock or power supplies. combining these feat ures provides a low-power, feature-rich and high- performance solution. security nonvolatile, flash-based proasic3l devices do not require a boot pr om, so there is no vulnerable external bitstream that can be eas ily copied. proasic3l devices inco rporate flashlock, which provides a unique combination of reprogrammability and desi gn security without external overhead, advantages that only an fpga with nonvolatile flash programming can offer. proasic3l devices utilize a 128-bit flash-based lock and a separate aes key to provide the highest level of protection in the fpga indus try for programmed intellectual pr operty and configuration data. in addition, all flashrom data in proasic3l devices c an be encrypted prior to loading, using the industry- leading aes-128 (fips192) bit block cipher encryption standa rd. aes was adopted by the national institute of standards and technology (nist) in 2000 and replaces the 1977 des standard. proasic3l devices have a built-in aes decrypti on engine and a flash-based ae s key that make them the most comprehensive programmable logic device security solution available today. proasic3l devices with aes-based security provide a high level of protection for remote field updates over public networks such as the internet, and are designed to ensure that valuable ip remains out of the hands of system overbuilders, system clon ers, and ip thieves. security, built into the fpga fabric, is an inheren t component of the proasi c3l family. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. the proasic3l family, with flashlock and aes security, is unique in being highly resi stant to both invasive and noninvasive attacks. your valuable ip is protected with industry-standard security, making remote isp possible. a proasic3l device provides the best available security for programmable logic designs. single chip flash-based fpgas store their configuration informati on in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga st ructure, and no external configuration data needs to be loaded at system power-up (unlike sram-based fpgas). therefore, flas h-based proasic3l fpgas do not require system configurati on components such as eeproms or mi crocontrollers to load device configuration data. this reduces bill-of-materials co sts and pcb area, and incr eases security and system reliability. instant on flash-based proasic3l devices support level 0 of th e instant on classificati on standard. this feature helps in system component initializa tion, execution of critical tasks be fore the processor wakes up, setup and configuration of memory blocks, clock genera tion, and bus activity management. the instant on feature of flash-based pr oasic3l devices greatly simplifies total system design and reduces total system cost, often eliminating the need for cplds and clock generation plls. in a ddition, glitches and brownouts in system power will not corrupt the pr oasic3l device's flash configuration, and unlike sram-based fpgas, the device will not have to be reloaded when system pow er is restored. this enables the reduction or complete removal of t he configuration prom, expensive voltage monitor, brownout detection, and clock generator devices fr om the pcb design. flash-based proasic3l devices simplify total system desig n and reduce cost and design risk while increasi ng system reliability and improving system initialization time.
proasic3l low power flash fpgas revision 13 1-3 reduced cost of ownership advantages to the designer extend beyond low unit cost, performance, and ease of use. unlike sram- based fpgas, flash-based proasic3l devices allow all functionality to be instant on; no external boot prom is required. on-boa rd security mechanisms prevent access to all the programming information and enable secure remote updates of the fpga logic. designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be comp romised or copied. secure isp can be performed using the industry- standard aes algorithm. the proasic3l family de vice architecture mitigates the need for asic migration at higher user volumes. this makes t he proasic3l family a cost-effective asic replacement solution, manipulation in portable media and secure communications, radio applications as well as high performance portable industrial, test, scientific and medical applications. firm-error immunity firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or i/o behavior in an unpredictable way. these errors are impossible to prevent in sram fpgas. the consequence of this type of error can be a complete system failure. fi rm errors do not exist in the configuration memory of proasic3l flash-based fpgas. once it is programmed, the flash cell configuration element of proasic3l fpgas cannot be altered by high-energy neutrons and is therefore im mune to them. recoverable (or soft) errors occur in the user data sram of all fpga devices. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric. advanced flash technology the proasic3l family offers many benefits, incl uding nonvolatility and reprogrammability, through an advanced flash-based, 130-nm lv cmos process with 7 layers of metal. standard cmos design techniques are used to implement logic and contro l functions. the combination of fine granularity, enhanced flexible routing resources, and abundant fl ash switches allows for very high logic utilization without compromising device routability or perform ance. logic functions within the device are interconnected through a four-level routing hierarchy. advanced architecture the proprietary proasic3l architec ture provides granularity comparable to standard-cell asics. the proasic3l device consists of five distinct and programmable architectural features ( figure 1-1 on page 1-4 and figure 1-2 on page 1-4 ): ? fpga versatiles ? dedicated flashrom ? dedicated sram/fifo memory ? extensive cccs and plls ? i/o structure the fpga core consists of a sea of versatiles. each versatile can be configured as a three-input logic function, a d-flip-flop (with or without enable), or a latch by progr amming the appropriate flash switch interconnections. the versatility of the proasic3l core tile, as eith er a three-input lookup table (lut) equivalent or a d-flip-flop/latch with enable, allows for efficient use of the fpga fabric. the versatile capability is unique to the proasic fa mily of third-generation- architecture flash fpgas. versatiles are connected with any of the four levels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, re configurable interconnect programming. maximum core utilization is possible for virtually any design.
proasic3l device family overview 1-4 revision 13 figure 1-1 ? proasic3l device architecture overview with four i/o banks (a3p250l, a3p600l, and a3p1000l) figure 1-2 ? proasic3el device architecture overview isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps ram block 4,608-bit dual-port sram or fifo block (a3p600l and a3p1000l) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 4,608-bit dual-port sram or fifo block versatile ram block ccc pro i/os 4,608-bit dual-port sram or fifo block ram block isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps
proasic3l low power flash fpgas revision 13 1-5 flash*freeze technology the proasic3l devices offer microsemi's proven flash*freeze technology, which enables designers to instantaneously shut off dynamic power consumption while retaining all sram and register information. flash*freeze technology enables the user to quickly (within 1 s) enter and ex it flash*freeze mode by activating the flash*freeze (ff) pin while all power s upplies are kept at their original values. in addition, i/os and global i/os can still be driven and can be toggling without impact on power consumption; clocks can still be driven or can be toggling without impact on power consumption; and the device retains all core registers, sram information, and states. i/o states are tristated during flash*freeze mode or can be set to a certain state using weak pull-up or pull-down i/o attribute configuration. no power is consumed by the i/o banks, clocks, jtag pins, or pll. flash*freeze technol ogy allows the user to switch to active mode on demand, thus si mplifying the power management of the device. the ff pin (active low) can be routed internally to t he core to allow the user's logic to decide when it is safe to transition to this mode. it is also possible to use the ff pin as a regular i/o if flash*freeze mode usage is not planned, which is advantageous becaus e of the inherent low-power static and dynamic capabilities of the proasic3l device. refer to figure 1-3 for an illustration of entering/exiting flash*freeze mode. versatiles the proasic3l core consists of versatiles, which have been enhanced beyond the proasic plus ? core tiles. the proasic3l versatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set refer to figure 1-4 for versatile configurations. figure 1-3 ? proasic3l flash*freeze mode figure 1-4 ? versatile configurations proasic3l fpga flash*freeze mode control flash*freeze pin x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
proasic3l device family overview 1-6 revision 13 user nonvolatile flashrom proasic3l devices have 1 kbit of on-chip, user-acce ssible, nonvolatile flashrom. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business models (for example, set-top boxes) ? secure key storage for secure communications algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written using the standard pr oasic3l ieee 1532 jtag programming interface.the core can be individually programmed (erased and written), and on-chip aes decryption can be used selectively to securely load data over public networks, as in security keys stored in the flashrom for a user design. the flashrom can be programmed via the jtag progr amming interface, and its contents can be read back either through the jtag programming interface or via direct fpga core addressing. note that the flashrom can only be programmed from the jtag interface and cannot be programmed from the internal logic array. the flashrom is programmed as 8 banks of 128 bits ; however, reading is performed on a byte-by-byte basis using a synchronous interface. a 7-bit address fr om the fpga core defines which of the 8 banks and which of the 16 bytes within that bank are being read. the three most significant bits (msbs) of the flashrom address determine the bank, and the four least significant bits (lsbs) of the flashrom address define the byte. the proasic3l development software solutions, libero soc and designer, have extensive support for the flashrom. one such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. anothe r feature allows the inclusion of static data for system version control. data for the flashrom can be generated qu ickly and easily using libero soc and designer software tools. comprehensive programming file support is also included to allow for easy programming of large numbers of part s with differing flashrom contents. sram and fifo proasic3l devices have embedded sram blocks along their north and south sides. each variable- aspect-ratio sram block is 4,608 bits in size. av ailable memory configurations are 25618, 5129, 1k4, 2k2, and 4k1 bits. the individual blocks have independent read and write ports that can be configured with different bit widths on each port. for ex ample, data can be sent through a 4-bit port and read as a single bitstream. the embedded sram bl ocks can be initialized via the device jtag port (rom emulation mode) using the ujtag macro. in addition, every sram block has an embedded fi fo control unit. the contro l unit allows the sram block to be configured as a synchronous fifo with out using additional core versatiles. the fifo width and depth are programmable. the fifo also feat ures programmable almost empty (aempty) and almost full (afull) flags in addition to the norma l empty and full flags. the embedded fifo control unit contains the counters necessary for generati on of the read and write address pointers. the embedded sram/fifo blocks can be cascaded to create larger configurations. pll and ccc proasic3l devices provide designers with flexible clock conditioning circuit (ccc) capabilities. each member of the proasic3l family contains six cccs. one ccc (center west side) has a pll. the six ccc blocks are locate d at the four corners an d the centers of the east and west sides. one ccc (center west side) has a pll. all six ccc blocks are usable; the four corner cccs and the east ccc allo w simple clock delay operations as well as clock spine access. the inputs of the six ccc blocks are accessible from the fpga core or from one of several inputs located near the ccc that have dedicated connections to the ccc block.
proasic3l low power flash fpgas revision 13 1-7 the ccc block has these key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz up to 250 mhz ? output frequency range (f out_ccc ) = 0.75 mhz up to 250 mhz ? 2 programmable delay types for clock skew minimization ? clock frequency synthesis additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270. output phase shift depends on the output divider configuration. ? output duty cycle = 50% 1.5% or better ? low output jitter: worst case < 2.5% clock per iod peak-to-peak period jitter when single global network used ? maximum acquisition time is 300 s ? exceptional tolerance to input period jitter? allowable input jitter is up to 1.5 ns ? four precise phases; maximum misalignment bet ween adjacent phases of 40 ps 250 mhz / f out_ccc global clocking proasic3l devices have extensive s upport for multiple clocking domains. in addition to the ccc and pll support described above, there is a comp rehensive global clock distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks. the versanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. i/os with advanced i/o standards the proasic3l family of fpgas feat ures a flexible i/o structure, su pporting a range of voltages (1.2 v, 1.5 v, 1.8 v, 2.5 v, 3.0 v wide range, and 3.3 v). pr oasic3l fpgas support different i/o standards, including single-ended, differential, and voltage-referenced (proasic3el only). the i/os are organized into banks, with two, four, or eight (proasic3el on ly) banks per device. the c onfiguration of these banks determines the i/o standards supported ( ta b l e 1 -1 ). for proasic3el, each i/o bank is subdivided into vref minibanks, which are used by voltage-referenced i/os. vref minibanks contain 8 to 18 i/os. all the i/os in a given minibank share a common vref li ne. therefore, if any i/o in a given vref minibank is configured as a vref pin, the remaining i/os in that minibank will be abl e to use that reference voltage. each i/o module contains several input, output, and enable registers. these registers allow the implementation of the following: ? single-data-rate applications (e.g., pci 66 mhz, bidirectional sstl 2 and 3, class i and ii) ? double-data-rate applications (e.g., ddr lvds, b-lvds, and m-lvds i/os for point-to-point communications, and ddr 200 mhz sram using bidirectional hstl class ii). proasic3l banks support lvpecl, lvds, b-lvds, and m-lvds. b-lvds and m-lvds can support up to 20 loads. table 1-1 ? i/o standards supported i/o bank type device and bank location i/o standards supported lvttl/ lvcmos pci/ pci-x lvpecl, lvds, b-lvds, m-lvds gtl+ 2.5 v/3.3 v, gtl 2.5 v/3.3 v, hstl i and ii, sstl2 i and ii, sstl3 i and ii pro i/os a3pe3000l 33 3 3 advanced i/os a3p250l, a3p600l, a3p1000l 33 3 not supported
proasic3l device family overview 1-8 revision 13 hot-swap (also called hot-plug, or hot-insertion) is t he operation of hot-insertion or hot-removal of a card in a powered-up system. cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. wide range i/o support proasic3l devices support jedec-defined wide rang e i/o operation. proasic3l devices support both the jesd8-b specification, covering 3 v and 3.3 v supplies, for an effective operating range of 2.7 v to 3.6 v, and jesd8-12 with its 1.2 v nominal, supporti ng an effective operating r ange of 1.14 v to 1.575 v. wider i/o range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components wit h greater tolerances. wide range eases i/o bank management and provides enhanc ed protection from system voltage sp ikes, while providing the flexibility to easily run custom voltage applications. specifying i/o states during programming you can modify the i/o states during programming in fl ashpro. in flashpro, this feature is supported for pdb files generated from designer v8.5 or greater. see the flashpro user?s guide for more information. note: pdb files generated from designer v8.1 to designer v8.4 (including all service packs) have limited display of pin numbers only. 1. load a pdb from the flashpro gui. you must have a pdb loaded to modify the i/o states during programming. 2. from the flashpro gui, click pdb configurat ion. a flashpoint ? pr ogramming file generator window appears. 3. click the specify i/o states during programming button to display the specify i/o states during programming dialog box. 4. sort the pins as desired by clicking any of the column headers to sort the entries by that header. select the i/os you wish to modify ( figure 1-5 on page 1-9 ). 5. set the i/o output state. you can set basic i/o se ttings if you want to use the default i/o settings for your pins, or use custom i/o settings to cust omize the settings for each pin. basic i/o state settings: 1 ? i/o is set to drive out logic high 0 ? i/o is set to drive out logic low last known state ? i/o is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming z -tri-state: i/o is tristated 6. click ok to return to the flashpoi nt ? programming file generator window. note: i/o states during programming are saved to the adb and resulting programming files after completing programming file generation.
proasic3l low power flash fpgas revision 13 1-9 figure 1-5 ? i/o states during programming window

revision 13 2-1 2 ? proasic3l dc and switching characteristics general specifications operating conditions stresses beyond those listed in ta b l e 2 - 1 may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of th e device at these or any other conditions beyond those listed under the recommended o perating conditions specified in table 2-2 on page 2-2 is not implied. table 2-1 ? absolute maximum ratings symbol parameter limits units vcc dc core supply voltage ?0.3 to 1.65 v vjtag jtag dc voltage ?0.3 to 3.75 v vpump programming voltage ?0.3 to 3.75 v vccpll analog power supply (pll) ?0.3 to 1.65 v vcci and vmv 2 dc i/o buffer supply voltage ?0.3 to 3.75 v vi i/o input voltage ?0.3 v to 3.6 v (when i/o hot insertion mode is enabled) ?0.3 v to (vcci + 1 v) or 3.6 v, whichever voltage is lower (when i/o hot-insertion mode is disabled) v t stg 3 storage temperature ?65 to +150 c t j 3 junction temperature +125 c notes: 1. the device should be operated within the limits specified by the datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 2-4 on page 2-3 . 2. vmv pins must be connected to the corresponding vcci pins. see the "vmvx i/o supply voltage (quiet)" section on page 3-1 for further information. 3. for flash programming and retention maximum limits, refer to table 2-3 on page 2-2 , and for recommended operating limits, refer to table 2-2 on page 2-2 .
proasic3l dc and switching characteristics 2-2 revision 13 table 2-2 ? recommended operating conditions 1 symbol parameter commercial industrial units t a ambient temperature 0 to +70 ?40 to +85 c t j junction temperature 0 to + 85 ?40 to +100 c vcc 2 1.2 v?1.5 v wide range core voltage 3 1.14 to 1.575 1.14 to 1.575 v vjtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v vpump 5 programming voltage programming mode 4 3.15 to 3.45 3.15 to 3.45 v operation 5 0 to 3.6 0 to 3.6 v vccpll 6 analog power supply (pll) 1.2 v?1.5 v wide range core voltage 3 1.14 to 1.575 1.14 to 1.575 v vcci and vmv 7 1.2 v dc supply voltage 8 1.14 to 1.26 1.14 to 1.26 v 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v wide range dc supply voltage 9 2.7 to 3.6 2.7 to 3.6 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v lvds differential i/o 2.375 to 2.625 2.375 to 2.625 v lvpecl differential i/o 3.0 to 3.6 3.0 to 3.6 v notes: 1. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 2. the ranges given here are for power supplies only. the recommended input voltage ranges specific to each i/o standard are given in table 2-14 on page 2-10 . vcci should be at the same voltage within a given i/o bank. 3. all proasic3l devices must be programmed with the vcc core voltage at 1.5 v. 4. the programming temperat ure range supported is t ambient = 0c to 85c. 5. vpump can be left floating during nor mal operation (not programming mode). 6. vccpll pins should be tied to vcc pins. see the "vccpla/b/c/d/e/f pll supply voltage" section on page 3-1 for further information. 7. vmv pins must be connected to the corresponding vcci pins. see the "vmvx i/o supply voltage (quiet)" section on page 3-1 for further information. 8. for proasic ? 3l devices, vcci ?? vcc. 9. 3.3 v wide range is compliant to the jesd8-a specification and supports 3.0 v vcci operation. table 2-3 ? flash programming limits ? retention, storage, and operating temperature 1 product grade programming cycles program retention (biased/unbiased) maximum storage temperature t stg (c) 2 maximum operating junction temperature t j (c) 2 commercial 500 20 years 110 100 industrial 500 20 years 110 100 notes: 1. this is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. these limits apply for program/data retention only. refer to table 2-1 on page 2-1 and table 2-2 for device operating conditions and absolute limits.
proasic3l low power flash fpgas revision 13 2-3 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is des igned into every proasic3 device. these circuits ensure easy transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any sequence with mi nimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 2-1 on page 2-4 and figure 2-2 on page 2-5 . there are five regions to consider during power-up. proasic3 i/os are activated only if all of the following three conditions are met: 1. vcc and vcci are above the minimum specified trip points ( figure 2-1 on page 2-4 and figure 2-2 on page 2-5 ). 2. vcci > vcc ? 0.75 v (typical) 3. chip is in the operating mode. v cci trip point: ramping up: 0.6 v < trip_point_up < 1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v v cc trip point: ramping up: 0.6 v < trip_point_up < 1.1 v ramping down: 0.5 v < trip_point_down < 1 v vcc and vcci ramp-up trip points are about 100 mv hi gher than ramp-down trip points. this specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tristated and weakly pulled up to vcci . ? jtag supply, pll power supplies, and charge pump vpump supply have no influence on i/o behavior. table 2-4 ? overshoot and undershoot limits 1 vcci average vcci?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at junction temperature at 85c. 2. the duration is allowed at one out of six clock cycl es. if the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 v. 3. this table does not provide pci overshoot/undershoot limits.
proasic3l dc and switching characteristics 2-4 revision 13 pll behavior at brownout condition microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. power ramp-up should be monotonic at least until vcc and vccplx exceed brownout activation levels. the vcc activation leve l is specified as 1.1 v worst-case (see figure 2-1 and figure 2- 2 on page 2-5 for more details). when pll power supply voltage and/or vcc levels dr op below the vcc brownout levels (0.75 v 0.25 v), the pll output lock signal goes low and/or the output clock is lost. refer to the "power-up/-down behavior of low-power flas h devices" chapter of the proasic3l fpga fabr ic user?s guide for information on clock and lock recovery. internal power-up activation sequence 1. core 2. input buffers output buffers, after 200 ns delay from input buffer activation. figure 2-1 ? v5 devices ? i/o state as a function of vcci and vcc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because vcci / vcc are below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. min vcci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v vcc vcc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v vcc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil, voh / vol, etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because vcci is below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. where vt can be from 0.58 v to 0.9 v (typically 0.75 v) vcci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification. vcc = vcci + vt
proasic3l low power flash fpgas revision 13 2-5 figure 2-2 ? v2 devices ? i/o state as a function of vcci and vcc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because vcci/vcc are below specification. for the same reason, input buffers do not meet vih/vil levels, and output buffers do not meet voh/vol levels. min vcci datasheet specification voltage at a selected i/o standard; i.e., 1.14 v,1.425 v, 1.7 v, 2.3 v, or 3.0 v vcc vcc = 1.14 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.2 v deactivation trip point: v d = 0.75 v 0.2 v activation trip point: v a = 0.9 v 0.15 v deactivation trip point: v d = 0.8 v 0.15 v vcc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil , voh / vol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because vcci is below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) vcci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification. vcc = vcci + vt
proasic3l dc and switching characteristics 2-6 revision 13 thermal characteristics introduction the temperature variable in the designer software re fers to the junction temperature, not the ambient temperature. this is an importan t distinction because dynamic and st atic power consumption cause the chip junction temperature to be hi gher than the ambi ent temperature. eq 1 can be used to calculate junction temperature. t j = junction temperature = ? t + t a eq 1 where: t a = ambient temperature ? t = temperature gradient between junction (silicon) and ambient ? t = ? ja * p ? ja = junction-to-ambient of the package. ? ja numbers are located in table 2-5 . p = power dissipation package thermal characteristics the device junction-to-case thermal resistivity is ? jc and the junction-to-ambient air thermal resistivity is ? ja . the thermal characteristics for ? ja are shown for two air flow rates. the absolute maximum junction temperature is 100c. eq 2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin fbga package at commercial temperature and in still air. eq 2 maximum power allowed max. junction temp. ( ? c) max. ambient temp. ( ? c) ? ? ja ( ? c/w) ------------------------------------------------------------------------------------------------------------------------------- ----------- 100 ? c70 ? c ? 20.5 ? c/w ------------------------------------- 1.463 w = = = table 2-5 ? package thermal resistivities package type device pin count ? jc ? ja units still air 200 ft./min. 500 ft./min. very thin quad flat pack (vqf p) all devices 100 10.0 35.3 29.4 27.1 c/w plastic quad flat pack (pqfp) all devices 208 8.0 26.1 22.5 20.8 c/w pqfp with embedded heatspreader all devices 208 3.8 16.2 13.3 11.9 c/w fine pitch ball grid array (fbga) a3p250l 144 12.2 43.8 37.7 35.8 c/w a3p600l 144 8.3 35.8 30.2 28.3 c/w a3p1000l 144 6.3 31.6 26.2 24.2 c/w a3p250l 256 12.0 38.6 34.7 33.0 c/w a3p600l 256 8.5 32.0 27.5 25.8 c/w a3p1000l 256 6.6 28.1 24.4 22.7 c/w agle3000 324 tbd tbd tbd tbd c/w a3p600l 484 9.5 27.5 21.9 20.2 c/w a3p1000l 484 8.0 23.3 19.0 16.7 c/w a3pe3000l 484 4.7 20.6 15.7 14.0 c/w a3pe3000l 896 2.4 13.6 10.4 9.4 c/w
proasic3l low power flash fpgas revision 13 2-7 temperature and voltage derating factors calculating power dissipation quiescent supply current quiescent supply current (i dd ) calculation depends on multiple factors, including operating voltages (vcc, vcci, and vjtag), operati ng temperature, system clock frequency, and power mode usage. microsemi recommends using the power calculator and smartpower software estimation tools to evaluate the projected static and active power bas ed on the user design, pow er mode usage, operating voltage, and temperature. table 2-6 ? temperature and voltage derati ng factors for timing delays (normalized to t j = 70c, vcc = 1.14 v) array voltage vcc (v) junction temperature (c) ?40c 0c 25c 70c 85c 110c 1.14 0.90 0.94 0. 96 1.00 1.01 1.03 1.2 0.870.900.920.960.970.99 1.26 0.83 0.86 0. 88 0.92 0.93 0.85 1.3 0.810.840.860.900.910.93 1.35 0.78 0.81 0. 83 0.87 0.88 0.89 1.4 0.750.780.800.830.840.86 1.425 0.74 0.77 0. 78 0.82 0.83 0.85 1.5 0.700.720.740.770.790.80 1.575 0.67 0.70 0. 72 0.75 0.76 0.77 table 2-7 ? power supply state per mode modes/power supplies power supply configurations vcc vccpll vcci vjtag vpump flash*freeze on on on on on/off/floating sleep off off on off off shutdown off off off off off no flash*freeze on on on on on/off/floating note: off: power supply level = 0 v table 2-8 ? quiescent supply current (idd) characte ristics, proasic3l flash*freeze mode* core voltage a3p250l a3p600l a3p1000l a3pe3000l units typical (25c) 1.2 v 0.33 0.55 0.88 2.75 ma 1.5 v 0.5 0.83 1.33 4.2 ma note: * idd includes vcc, vpump, vcci, vjtag, and vccpll currents.
proasic3l dc and switching characteristics 2-8 revision 13 table 2-9 ? quiescent supply current (idd) char acteristics, proa sic3l sleep mode* icci current core voltage a3p250l a3p600l a3p1000l a3pe3000l units vcci/vjtag = 1.2 v (per bank) typical (25c) 1.2 v 1.7 1.7 1.7 1.7 a vcci/vjtag = 1.5 v (per bank) typical (25c) 1.2 v/1.5 v 1.8 1.8 1.8 1.8 a vcci/vjtag = 1.8 v (per bank) typical (25c) 1.2 v/1.5 v 1.9 1.9 1.9 1.9 a vcci/vjtag = 2.5 v (per bank) typical (25c) 1.2 v/1.5 v 2.2 2.2 2.2 2.2 a vcci/vjtag = 3.3 v (per bank) typical (25c) 1.2 v/1.5 v 2.5 2.5 2.5 2.5 a note: *idd = n banks * icci table 2-10 ? quiescent supply current (idd) characteristics, shutdown mode core voltage a3pe3000l units typical (25c) 1.2 v/1.5 v 0 a table 2-11 ? quiescent supply current (idd) char acteristics, no flash*freeze mode 1 core voltage a3p250l a3p600l a3p1000l a3pe3000l units icca current 2 typical (25c) 1.2 v 0.33 0.55 0.88 2.75 ma 1.5 v 0.5 0.83 1.33 4.2 ma icci or ijtag current vcci/vjtag = 1.2 v (per bank) typical (25c) 1.2 v 1.7 1.7 1.7 1.7 a vcci/vjtag = 1.5 v (per bank) typical (25c) 1.2 v/1.5 v 1.8 1.8 1.8 1.8 a vcci/vjtag = 1.8 v (per bank) typical (25c) 1.2 v/1.5 v 1.9 1.9 1.9 1.9 a vcci/vjtag = 2.5 v (per bank) typical (25c) 1.2 v/1.5 v 2.2 2.2 2.2 2.2 a vcci/vjtag = 3.3 v (per bank) typical (25c) 1.2 v/1.5 v 2.5 2.5 2.5 2.5 a notes: 1. *idd = n banks * icci+icca. jtag counts as one bank when powered. 2. includes vcc and vpump and vccpll currents.
proasic3l low power flash fpgas revision 13 2-9 power per i/o pin table 2-12 ? summary of i/o input buffe r power (per pin) ? defa ult i/o software settings applicable to pro i/o banks vcci (v) static power pdc6 (mw) 1 dynamic power pac9 (w/mhz) 2 single-ended 3.3 v lvttl/lvcmos 3.3 ? 16.34 3.3 v lvttl/lvcmos ? schmitt trigger 3.3 ? 24.49 2.5 v lvcmos 2.5 ? 4.71 2.5 v lvcmos ? schmitt trigger 2.5 ? 6.13 1.8 v lvcmos 1.8 ? 1.66 1.8 v lvcmos ? schmitt trigger 1.8 ? 1.78 1.5 v lvcmos (jesd8-11) 1.5 ? 1.01 1.5 v lvcmos (jesd8-11) ? schmitt trigger 1.5 ? 0.97 1.2 v lvcmos 1.2 ? 0.60 1.2 v lvcmos ? schmitt trigger 1.2 ? 0.53 3.3 v pci 3.3 ? 17.76 3.3 v pci ? schmitt trigger 3.3 ? 19.10 3.3 v pci-x 3.3 ? 17.76 3.3 v pci-x ? schmitt trigger 3.3 ? 19.10 voltage-referenced 3.3 v gtl 3.3 2.90 7.07 2.5 v gtl 2.5 2.13 3.62 3.3 v gtl+ 3.3 2.81 2.97 2.5 v gtl+ 2.5 2.57 2.55 hstl (i) 1.5 0.17 0.85 hstl (ii) 1.5 0.17 0.85 sstl2 (i) 2.5 1.38 3.30 sstl2 (ii) 2.5 1.38 3.30 sstl3 (i) 3.3 3.21 8.08 sstl3 (ii) 3.3 3.21 8.08 differential lvds 2.5 2.26 0.95 lvpecl 3.3 5.71 1.62 notes: 1. pdc6 is the static power (where applicable) measured on vcci. 2. pac9 is the total dynamic power measured on vcci.
proasic3l dc and switching characteristics 2-10 revision 13 table 2-13 ? summary of i/o input buffe r power (per pin) ? defa ult i/o software settings 1 applicable to advanced i/o banks vcci (v) static power pdc6 (mw) 2 dynamic power pac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 16.22 2.5 v lvcmos 2.5 ? 4.65 1.8 v lvcmos 1.8 ? 1.65 1.5 v lvcmos (jesd8-11) 1.5 ? 0.98 1.2 v lvcmos 1.2 ? 0.61 3.3 v pci 3.3 ? 17.64 3.3 v pci-x 3.3 ? 17.64 differential lvds 2.5 2.26 0.95 lvpecl 3.3 5.72 1.63 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. p dc6 is the static power (where applicable) measured on vcci. 3. p ac10 is the total dynamic power measured on vcci. table 2-14 ? summary of i/o input buffe r power (per pin) ? defa ult i/o software settings applicable to standard plus i/o banks vcci (v) static power pdc6 (mw) 1 dynamic power pac9 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 16.23 2.5 v lvcmos 2.5 ? 4.66 1.8 v lvcmos 1.8 ? 1.64 1.5 v lvcmos (jesd8-11) 1.5 ? 0.99 1.2 v lvcmos 1.2 ? 0.58 3.3 v pci 3.3 ? 17.64 3.3 v pci-x 3.3 ? 17.64 notes: 1. pdc6 is the static power (where applicable) measured on vcci. 2. pac9 is the total dynamic power measured on vcci.
proasic3l low power flash fpgas revision 13 2-11 table 2-15 ? summary of i/o output bu ffer power (per pin) ? de fault i/o softw are settings 1 applicable to pro i/os c load (pf) vcci (v) static power pdc7 (mw) 2 dynamic power pac10 (w/mhz) 3 single-ended 3.3 v lvttl/lvcmos 5 3.3 ? 148.00 2.5 v lvcmos 5 2.5 ? 83.23 1.8 v lvcmos 5 1.8 ? 54.58 1.5 v lvcmos (jesd8-11) 5 1.5 ? 37.05 1.2 v lvcmos 5 1.2 ? 17.94 3.3 v pci 10 3.3 ? 204.61 3.3 v pci-x 10 3.3 ? 204.61 voltage-referenced 3.3 v gtl 10 3.3 ? 24.08 2.5 v gtl 10 2.5 ? 13.52 3.3 v gtl+ 10 3.3 ? 24.10 2.5 v gtl+ 10 2.5 ? 13.54 hstl (i) 20 1.5 7.08 26.22 hstl (ii) 20 1.5 13.88 27.22 sstl2 (i) 30 2.5 16.69 105.56 sstl2 (ii) 30 2.5 25.91 116.60 sstl3 (i) 30 3.3 26.02 114.87 sstl3 (ii) 30 3.3 42.21 131.76 differential lvds ? 2.5 7.70 89.62 lvpecl ? 3.3 19.42 168.02 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. pdc7 is the static power (where applicable) measured on vcci. 3. pac10 is the total dynamic power measured on vcci.
proasic3l dc and switching characteristics 2-12 revision 13 table 2-16 ? summary of i/o output bu ffer power (per pin) ? de fault i/o softw are settings 1 applicable to advanced i/o banks c load (pf) vcci (v) static power pdc7 (mw) 2 dynamic power pac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 5 3.3 ? 141.97 2.5 v lvcmos 5 2.5 ? 79.98 1.8 v lvcmos 5 1.8 ? 52.26 1.5 v lvcmos (jesd8-11) 5 1.5 ? 35.62 1.2 v lvcmos 5 1.2 ? 21.29 3.3 v pci 10 3.3 ? 201.02 3.3 v pci-x 10 3.3 ? 201.02 differential lvds ? 2.5 7.74 89.71 lvpecl ? 3.3 19.54 167.54 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. pdc7 is the static power (where applicable) measured on vcci. 3. pac10 is the total dynamic power measured on vcci. table 2-17 ? summary of i/o output bu ffer power (per pin) ? de fault i/o softw are settings 1 applicable to standard plus i/o banks c load (pf) vcci (v) static power pdc7 (mw) 2 dynamic power pac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 5 3.3 ? 125.97 2.5 v lvcmos 5 2.5 ? 70.82 1.8 v lvcmos 5 1.8 ? 36.39 1.5 v lvcmos (jesd8-11) 5 1.5 ? 25.34 1.2 v lvcmos 5 1.2 ? 16.24 3.3 v pci 10 3.3 ? 184.92 3.3 v pci-x 10 3.3 ? 184.92 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. pdc7 is the static power (where applicable) measured on vcci. 3. pac10 is the total dynamic power measured on vcci.
proasic3l low power flash fpgas revision 13 2-13 power consumption of vari ous internal resources table 2-18 ? different components contributing to dynamic power consumption in proasic3l devices at 1.2 v vcc parameter definition device specific dynamic power (w/mhz) a3pe3000l a3p1000l a3p600l a3p250l pac1 clock contribution of a global rib 12.61 9.28 8.19 7.07 pac2 clock contribution of a global spine 2.66 1.59 1.19 1.01 pac3 clock contribution of a versatile row 0.56 0.52 pac4 clock contribution of a versatile used as a sequential module 0.07 pac5 first contribution of a versatile used as a sequential module 0.05 pac6 second contribution of a versatile used as a sequential module 0.19 pac7 contribution of a versatile used as a combinatorial module 0.11 pac8 average contribution of a routing net 0.45 pac9 contribution of an i/o in put pin (standard-dependent) see table 2-12 on page 2-9 . through table 2-14 on page 2-10 . pac10 contribution of an i/o outp ut pin (standard-dependent) see table 2-15 on page 2-11 through table 2-17 on page 2-12 . pac11 average contribution of a ram block during a read operation 25.00 pac12 average contribution of a ram block during a write operation 30.00 pac13 dynamic contribution for pll 1.74 note: *for a different output load, drive strength, or slew rate, microsemi recommends using the microsemi power spreadsheet calculator or smartpower tool in libero soc.
proasic3l dc and switching characteristics 2-14 revision 13 table 2-19 ? different components contributing to dynamic power consumption in proasic3l devices at 1.5 v vcc parameter definition device specific dynamic power (w/mhz) a3pe3000l a3p1000l a3p600l a3p250l pac1 clock contribution of a global rib 19.7 14.50 12.80 11.00 pac2 clock contribution of a global spine 4.16 2.48 1.85 1.58 pac3 clock contribution of a versatile row 0.88 0.81 pac4 clock contribution of a versatile used as a sequential module 0.12 pac5 first contribution of a versatile used as a sequential module 0.07 pac6 second contribution of a versatile used as a sequential module 0.29 pac7 contribution of a versatile used as a combinatorial module 0.29 pac8 average contribution of a routing net 0.70 pac9 contribution of an i/o in put pin (standard-dependent) see table 2-12 on page 2-9 . through table 2-14 on page 2-10 . pac10 contribution of an i/o outp ut pin (standard-dependent) see table 2-15 on page 2-11 through table 2-17 on page 2-12 . pac11 average contribution of a ram block during a read operation 25.00 pac12 average contribution of a ram block during a write operation 30.00 pac13 dynamic contribution for pll 2.60 note: *for a different output load, drive strength, or slew rate, microsemi recommends using the microsemi power spreadsheet calculator or smartpower tool in libero soc. table 2-20 ? different componen ts contributing to the static power consumption in proasic3l devices parameter definition device specific dynamic power (w) a3pe3000l a3p1000l a3p600l a3p250l pdc1 array static power in active mode see table 2-11 on page 2-8 . pdc2 array static power in static (idle) mode see table 2-9 on page 2-8 . pdc3 array static power in flash*freeze mode see table 2-8 on page 2-7 . pdc4 static pll contribution at 1.2 v core (operating mode only) 1.42 mw static pll contribution at 1.5 v core (operating mode only) 2.55 mw pdc5 bank quiescent power (vcci-dependent) see table 2-8 on page 2-7 , table 2-9 on page 2-8 , table 2-11 on page 2-8 . pdc6 i/o input pin static power (standard-dependent) see table 2-12 on page 2-9 through table 2-14 on page 2-10 . pdc7 i/o output pin static power (standard-dependent) see table 2-15 on page 2-11 through table 2-17 on page 2-12 . note: *for a different output load, drive strength, or sl ew rate, microsemi recommends using the microsemi power spreadsheet calculator or smar tpower tool in libero soc.
proasic3l low power flash fpgas revision 13 2-15 power calculation methodology this section describes a simplified method to estima te power consumption of an application. for more accurate and detailed power estimations, use the smartpower tool in libero soc software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number a nd the frequency of each output clock generated ? the number of combinatorial and sequential cells used in the design ? the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 2-21 on page 2-17 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-22 on page 2-17 . ? read rate and write rate to the memory?guidel ines are provided for typical applications in table 2-22 on page 2-17 . the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat p stat = (pdc1 or pdc2 or pdc3) + n banks * pdc5 + n inputs * pdc6 + n outputs * pdc7 n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. n banks is the number of i/o banks powered in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (pac1 + n spine * pac2 + n row * pac3 + n s-cell * pac4) * f clk n spine is the number of global spines used in the user design?guidelines are provided in the "spine architecture" section of the proasic3l fpga fabric user?s guide . n row is the number of versatile rows used in the design?guidelines are provided in the "spine architecture" section of the proasic3l fpga fabric user?s guide . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. pac1, pac2, pac3, and pac4 are device-dependent. sequential cells contribution?p s-cell p s-cell = n s-cell * (pac5 + ? 1 / 2 * pac6) * f clk n s-cell is the number of versatiles used as sequential modules in the design. when a multi-tile sequential cell is used, it should be accounted for as 1. ? 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-21 on page 2-17 . f clk is the global clock signal frequency.
proasic3l dc and switching characteristics 2-16 revision 13 combinatorial cells contribution?p c-cell p c-cell = n c-cell * ? 1 / 2 * pac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. ? 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-21 on page 2-17 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * ? 1 / 2 * pac8 * f clk n s-cell is the number of versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. ? 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-21 on page 2-17 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * ? 2 / 2 * pac9 * f clk n inputs is the number of i/o input buffers used in the design. ? 2 is the i/o buffer toggle rate?guidelines are provided in table 2-21 on page 2-17 . f clk is the global clock signal frequency. i/o output buffer contribution?p outputs p outputs = n outputs * ? 2 / 2 * ? 1 * pac10 * f clk n outputs is the number of i/o output buffers used in the design. ? 2 is the i/o buffer toggle rate?guidelines are provided in table 2-21 on page 2-17 . ? 1 is the i/o buffer enable rate?guidelines are provided in table 2-22 on page 2-17 . f clk is the global clock signal frequency. ram contribution?p memory p memory = pac11 * n blocks * f read-clock * ? 2 + pac12 * n block * f write-clock * ? 3 n blocks is the number of ram blocks used in the design. f read-clock is the memory read clock frequency. ? 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. ? 3 is the ram enable rate for write operations?guidelines are provided in table 2-22 on page 2-17 . pll contribution?p pll p pll = pdc4 + pac13 * f clkout f clkout is the output clock frequency. 1 1. if a pll is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (p ac13 * f clkout product) to the total pll contribution.
proasic3l low power flash fpgas revision 13 2-17 guidelines toggle rate definition a toggle rate defines the frequency of a net or logic elem ent relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 enable rate definition output enable rate is the average percentage of ti me during which tristate outputs are enabled. when nontristate output buffers are used, the enable rate should be 100%. table 2-21 ? toggle rate guidelines recommended for power calculation component definition guideline ? 1 toggle rate of versatile outputs 10% ? 2 i/o buffer toggle rate 10% table 2-22 ? enable rate guidelines reco mmended for power calculation component definition guideline ? 1 i/o output buffer enable rate 100% ? 2 ram enable rate for read operations 12.5% ? 3 ram enable rate for write operations 12.5%
proasic3l dc and switching characteristics 2-18 revision 13 user i/o characteristics timing model figure 2-3 ? timing model operating conditions: ?1 speed, commercial temperature range (t j = 70c), worst-case v cc =1.14v dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvpecl (applicable to advanced i/o banks only)l lvpecl (applicable to advanced i/o banks only) lvds, blvds, m-lvds (applicable for advanced i/o banks only) lvttl 3.3 v output drive strength = 12 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 4 ma high slew rate lvttl output drive strength = 12 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 0.56 ns t pd = 0.49 ns t dp = 1.34 ns t pd = 0.87 ns t dp = 2.64 ns (advanced i/o banks) t pd = 0.47 ns t dp = 3.66 ns (advanced i/o banks) t pd = 0.47 ns t dp = 3.97 ns (advanced i/o banks) t pd = 0.47 ns t py = 0.76 ns (advanced i/o banks) t clkq = 0.55 ns t oclkq = 0.59 ns t sud = 0.43 ns t osud = 0.31 ns t dp = 2.64 ns (advanced i/o banks) t py = 0.76 ns (advanced i/o banks) t py = 1.20 ns t clkq = 0.55 ns t sud = 0.43 ns t py = 0.76 ns (advanced i/o banks) t iclkq = 0.24 ns t isud = 0.26 ns t py = 1.05 ns
proasic3l low power flash fpgas revision 13 2-19 figure 2-4 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50% 50% vih vcc vil t din (r) din gnd t din (f) 50% 50% vcc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
proasic3l dc and switching characteristics 2-20 revision 13 figure 2-5 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) vtrip vtrip voh vcc d 50% 50% vcc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
proasic3l low power flash fpgas revision 13 2-21 figure 2-6 ? tristate output buffer timing model and delays (example) d clk q d clk q 10% v cci t zl vtrip 50% t hz 90% vcci t zh vtrip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout d i/o interface e t eout t zls vtrip 50% t zhs vtrip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% vcc vcc vcc vcci vcc vcc vcc voh vol vol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f))
proasic3l dc and switching characteristics 2-22 revision 13 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-23 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?s oftware default settings applicable to pro i/o banks i/o standard drive strength (ma) equiv. software default drive strength option 1 slew rate vil vih vol voh iol 3 ioh 3 min. v max. v min. v max. 2 v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 v lvcmos wide range 4 100 a 12 ma high ?0.3 0.8 2 3.6 0.2 vcci ? 0.2 0.1 0.1 2.5 v lvcmos 12 ma 12 ma high ?0.3 0.7 1. 7 2.7 0.7 1.7 12 12 1.8 v lvcmos 12 ma 12 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 12 12 1.5 v lvcmos 12 ma 12 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 12 12 1.2 v lvcmos 2 ma 2 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.26 0.25 * vcci 0.75 * vcci 2 2 1.2 v lvcmos wide range 5 100 a 2 ma high ?0.3 0.3 * vcci 0.7 * vcci 1.575 0.1 vcci ? 0.1 0.1 0.1 3.3 v pci per pci specification 3.3 v pci-x per pci-x specification 3.3 v gtl 20 ma 6 20 ma 6 high ?0.3 vref ? 0.05 vref + 0.05 3.6 0.4 ? 20 20 2.5 v gtl 20 ma 6 20 ma 6 high ?0.3 vref ? 0.05 vref + 0.05 2.7 0.4 ? 20 20 3.3 v gtl+ 35 ma 35 ma high ?0.3 vref ? 0.1 vref + 0.1 3.6 0.6 ? 35 35 2.5 v gtl+ 33 ma 33 ma high ?0.3 vref ? 0.1 vref + 0.1 2.7 0.6 ? 33 33 hstl (i) 8 ma 8 ma high ?0.3 vref ? 0.1 vref + 0.1 1.575 0.4 vcci ? 0.4 8 8 hstl (ii) 15 ma 6 15 ma 6 high ?0.3 vref ? 0.1 vref + 0.1 1.575 0.4 vcci ? 0.4 15 15 sstl2 (i) 15 ma 15 ma high ?0.3 vref ? 0.1 vref + 0.1 2.7 0.54 vcci ? 0.62 15 15 sstl2 (ii) 18 ma 18 ma high ?0.3 vref ? 0.1 vref + 0.1 2.7 0.35 vcci ? 0.43 18 18 sstl3 (i) 14 ma 14 ma high ?0.3 vref ? 0.1 vref + 0.1 3.6 0.7 vcci ? 1.1 14 14 sstl3 (ii) 21 ma 21 ma high ?0.3 vref ? 0.1 vref + 0.1 3.6 0.5 vcci ? 0.9 21 21 notes: 1. please note that 1.2v lvcmos and 3.3v lvcmos wide range is applicable to 100ua drive strength only. the configuration will not operate at the equivalent software. 2. maximum vih is 3.6 v for all i/o standards with hot-insertion is enabled. 3. currents are measured at 85c junction temperature. 4. all lvcmos 3.3 v software macros support lvcmos 3. 3 v wide range as specified in the jesd-8b specification. 5. all lvcmos 1.2 v software macros support lvcmos 1. 2 v wide range as specified in the jesd8-12 specification. 6. output drive strength is below jedec specification. 7. output slew rate can be extracted using the ibis models.
proasic3l low power flash fpgas revision 13 2-23 table 2-24 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?s oftware default settings applicable to advanced i/o banks i/o standard drive strength equiv. software default drive strength option 1 slew rate vil vih vol voh iol 2 ioh 2 min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 v lvcmos wide range 3 100 a 12 ma high ?0.3 0.8 2 3.6 0.2 vcci ? 0.2 0.1 0.1 2.5 v lvcmos 12 ma 12 ma high ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 v lvcmos 12 ma 12 ma high ?0.3 0.35 * vcci 0. 65 * vcci 1.9 0.45 vcci ? 0.45 12 12 1.5 v lvcmos 12 ma 12 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 12 12 1.2 v lvcmos 2 ma 2 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.26 0.25 * vcci 0.75 * vcci 2 2 1.2 v lvcmos wide range 4,5 100 a 2 ma high ?0.3 0.3 * vcci 0. 7 * vcci 1.575 0.1 vcci ? 0.1 0.1 0.1 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications notes: 1. please note that 1.2 v lvcmos and 3.3 v lvcmos wide range is applicable to 100 a drive strength only. the configuration will not operate at the equivalent software. 2. currents are measured at 85c junction temperature. 3. all lvcmos 3.3 v software macros support lvcmos 3. 3 v wide range as specified in the jesd-8b specification. 4. all lvcmos 1.2 v software macros support lvcmos 1. 2 v wide range as specified in the jesd8-12 specification. 5. applicable to devices operating at vcci vcc. 6. output slew rate can be extracted using the ibis models.
proasic3l dc and switching characteristics 2-24 revision 13 table 2-25 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?s oftware default settings applicable to standard plus i/o banks i/o standard drive strength equiv. software default drive strength option 1 slew rate vil vih vol voh iol 2 ioh 2 min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 v lvcmos wide range 3 100 a 12 ma high ?0.3 0.8 2 3.6 0.2 vcci ? 0.2 0.1 0.1 2.5 v lvcmos 12 ma 12 ma high ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 v lvcmos 8 ma 8 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 8 8 1.5 v lvcmos 4 ma 4 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 4 4 1.2 v lvcmos 4 2 ma 2 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.26 0.25 * vcci 0.75 * vcci 2 2 1.2 v lvcmos wide range 4,5 100 a 2 ma high ?0.3 0.3 * vcci 0.7 * vcci 1.575 0.1 vcci ? 0.1 0.1 0.1 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications notes: 1. please note that 1.2 v lvcmos and 3.3 v lvcmos wide range is applicable to 100 a drive strength only. the configuration will not operate at the equivalent software. 2. currents are measured at 85c junction temperature. 3. all lvcmos 3.3 v software macros support lvcmos 3. 3 v wide range as specified in the jesd-8b specification. 4. all lvcmos 1.2 v software macros support lvcmos 1. 2 v wide range as specified in the jesd8-12 specification. 5. applicable to devices operating at vcci vcc. 6. output slew rate can be extracted using the ibis models.
proasic3l low power flash fpgas revision 13 2-25 table 2-26 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions dc i/o standard commercial 1 industrial 2 iil iih iil 3 iih 4 a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 3.3 v lvcmos wide range 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 1.2 v lvcmos 5 10 10 15 15 1.2 v lvcmos wide range 5 10 10 15 15 3.3 v pci 10 10 15 15 3.3 v pci-x 10 10 15 15 3.3 v gtl 10 10 15 15 2.5 v gtl 10 10 15 15 3.3 v gtl+ 10 10 15 15 2.5 v gtl+ 10 10 15 15 hstl (i) 10 10 15 15 hstl (ii) 10 10 15 15 sstl2 (i) 10 10 15 15 sstl2 (ii) 10 10 15 15 sstl3 (i) 10 10 15 15 sstl3 (ii) 10 10 15 15 notes: 1. commercial range (0c < t a < 70c) 2. industrial range (?40c < t a < 85c) 3. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3v < vin proasic3l dc and switching characteristics 2-26 revision 13 summary of i/o timing characte ristics ? default i/o software settings table 2-27 ? summary of ac measuring points standard input reference voltage (vref_typ) board termination voltage (vtt_ref) measuring trip point (vtrip) 3.3 v lvttl / 3.3 v lvcmos ? ? 1.4 v 3.3 v lvcmos wide range ? ? 1.4 v 2.5 v lvcmos ? ? 1.2 v 1.8 v lvcmos ? ? 0.90 v 1.5 v lvcmos ? ? 0.75 v 1.2 v lvcmos * ? ? 0.6 v 1.2 v lvcmos wide range* ? ? 0.6 v 3.3 v pci ? ? 0.285 * vcci (rr) 0.615 * vcci (ff)) 3.3 v pci-x ? ? 0.285 * vcci (rr) 0.615 * vcci (ff) 3.3 v gtl 0.8 v 1.2 v vref 2.5 v gtl 0.8 v 1.2 v vref 3.3 v gtl+ 1.0 v 1.5 v vref 2.5 v gtl+ 1.0 v 1.5 v vref hstl (i) 0.75 v 0.75 v vref hstl (ii) 0.75 v 0.75 v vref sstl2 (i) 1.25 v 1.25 v vref sstl2 (ii) 1.25 v 1.25 v vref sstl3 (i) 1.5 v 1.485 v vref sstl3 (ii) 1.5 v 1.485 v vref lvds ? ? cross point lvpecl ? ? cross point note: *applicable only to devices oper ating in the 1.2 v core range. table 2-28 ? i/o ac parameter definitions parameter parameter definition t dp data to pad delay through the output buffer t py pad to data delay through the input buffer t dout data to output buffer delay through the i/o interface t eout enable to output buffer tristate c ontrol delay through the i/o interface t din input buffer to data delay through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low
proasic3l low power flash fpgas revision 13 2-27 1.5 v dc core voltage table 2-29 ? summary of i/o timing character istics?software default settings ?1 speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.425v, worst case vcci pro i/o banks standard drive strength (ma) equiv. software default drive strength option 1 slew rate capacitive load (pf) external resistor ( ? ) t dout (ns) t dp (ns) t din (ns) t py (ns) t pys (ns) te o ut (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high 5 ? 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns 3.3 v lvcmos wide range 1,2 100 a 12 ma high 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ns 2.5 v lvcmos 12 ma 12 ma high 5 ? 0.50 1.92 0. 03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns 1.8 v lvcmos 12 ma 12 ma high 5 ? 0.50 2.14 0. 03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns 1.5 v lvcmos 12 ma 12 ma high 5 ? 0.50 2.46 0. 03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns 3.3 v pci per pci spec. ? high 5 25 3 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns 3.3 v pci-x per pci-x spec. ? high 10 25 3 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns 3.3 v gtl 20 ma 5 20 ma 5 high 10 25 0.50 1.59 0.03 1.80 ? 0.33 1.56 1.59 ? ? 3.27 3.30 ns 2.5 v gtl 20 ma 5 20 ma 5 high 10 25 0.50 1.63 0.03 1.75 ? 0.33 1.66 1.63 ? ? 3.37 3.34 ns 3.3 v gtl+ 35 ma 35 ma high 10 25 0.50 1.57 0.03 1.80 ? 0.33 1.60 1.57 ? ? 3.31 3.29 ns 2.5 v gtl+ 33 ma 33 ma high 10 25 0.50 1.69 0.03 1.75 ? 0.33 1.72 1.61 ? ? 3.43 3.32 ns hstl (i) 8 ma 8 ma high 20 25 0.50 2.43 0.03 2.12 ? 0.33 2.48 2.41 ? ? 4.19 4.12 ns hstl (ii) 15 ma 5 15 ma high 20 50 0.50 2.32 0.03 2.12 ? 0.33 2.36 2.08 ? ? 4.07 3.79 ns sstl2 (i) 15 ma 15 ma high 30 25 0.50 1.63 0.03 1.61 ? 0.33 1.66 1.41 ? ? 1.66 1.41 ns sstl2 (ii) 18 ma 18 ma high 30 50 0.50 1.66 0.03 1.61 ? 0.33 1.69 1.36 ? ? 1.69 1.36 ns sstl3 (i) 14 ma 14 ma high 30 25 0.50 1.77 0.03 1.54 ? 0.33 1.80 1.41 ? ? 1.80 1.41 ns sstl3 (ii) 21 ma 21 ma high 30 50 0.50 1.58 0.03 1.54 ? 0.33 1.61 1.28 ? ? 1.61 1.28 ns lvds 24 ma 24 ma high ? ? 0.50 1.40 0.03 1.85 ? ? ? ? ? ? ? ? ns lvpecl 24 ma 24 ma high ? ? 0.50 1.40 0.03 1.67 ? ? ? ? ? ? ? ? ns notes: 1. the minimum drive strength for any lvcmos 1.2 v or lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jesd8-b specification. 3. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-12 on page 2-81 for connectivity. this resistor is not required during normal operation. 4. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. 5. output drive strength is below jedec specification.
proasic3l dc and switching characteristics 2-28 revision 13 table 2-30 ? summary of i/o timing character istics?software default settings ?1 speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.425 v, worst case vcci advanced i/o banks i/o standard drive strength (ma) equiv. software default drive strength option 1 slew rate capacitive load (pf) external resistor ( ? ) t dout (ns) t dp (ns) t din (ns) t py (ns) te o ut (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high 5 ? 0.46 1.83 0.03 0. 78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns 3.3 v lvcmos wide range 1,2 100 a 12 ma high 5 ? ? ? ? ? ? ? ? ? ? ? ? ns 2.5 v lvcmos 12 ma 12 ma high 5 ? 0.46 1. 85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns 1.8 v lvcmos 12 ma 12 ma high 5 ? 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns 1.5 v lvcmos 12 ma 12 ma high 5 ? 0.46 2.33 0.03 1.10 0.33 2.37 2.01 3.02 3.22 4.08 3.72 ns 3.3 v pci per pci spec. ? high 5 25 3 0.46 2.05 0.03 0.66 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns 3.3 v pci-x per pci-x spec. ? high 10 25 3 0.46 2.05 0.03 0.64 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns lvds 24 ma ? high ? ? 0.46 1.40 0.03 1.23 n/a n/a n/a n/a n/a n/a n/a ns lvpecl 24 ma ? high ? ? 0.46 1.38 0.03 1.08 n/a n/a n/a n/a n/a n/a n/a ns notes: 1. the minimum drive strength for any lvcmos 1.2 v or lvcm os 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jesd8-b specification. 3. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-12 on page 2-81 for connectivity. this resistor is not required during normal operation. 4. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-29 table 2-31 ? summary of i/o timing character istics?software default settings ?1 speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.425 v, worst case vcci = 3.0 v standard plus i/o banks i/o standard drive strength (ma) equiv. software default drive strength option 1 slew rate capacitive load (pf) external resistor t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high 5 ? 0.46 1.56 0.03 0. 77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns 3.3 v lvcmos wide range 1,2 100 a 12 ma high 5 ? ? ? ? ? ? ? ? ? ? ? ? ns 2.5 v lvcmos 12 ma 12 ma high 5 ? 0.46 1. 59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns 1.8 v lvcmos 8 ma 8 ma high 5 ? 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2. 16 2.38 3.33 3.03 ns 1.5 v lvcmos 4 ma 4 ma high 5 ? 0.46 2.15 0.03 1.09 0.33 2.19 1.82 2. 32 2.40 3.90 3.53 ns 3.3 v pci per pci spec. ? high 10 25 3 0.46 1.77 0.03 0.65 0.33 1.80 1. 31 2.14 2.47 3.51 3.02 ns 3.3 v pci-x per pci-x spec. ? high 10 25 3 0.46 1.77 0.03 0.64 0.33 1.80 1. 31 2.14 2.47 3.51 3.02 ns notes: 1. the minimum drive strength for any lvcmos 1.2 v or lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jesd8-b specification. 3. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-12 on page 2-81 for connectivity. this resistor is not required during normal operation. 4. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-30 revision 13 1.2 v dc core voltage table 2-32 ? summary of i/o timing character istics?software default settings ?1 speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.14 v, worst case vcci pro i/o banks standard drive strength (ma) equiv. software default drive strength option 1 slew rate capacitive load (pf) external resistor ( ? ) t dout (ns) t dp (ns) t din (ns) t py (ns) t pys (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high 5 ? 0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns 3.3 v lvcmos wide range 1,2 100 a12 mahigh5?????????????ns 2.5 v lvcmos 12 ma 12 ma high 5 ? 0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns 1.8 v lvcmos 12 ma 12 ma high 5 ? 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns 1.5 v lvcmos 12 ma 12 ma high 5 ? 0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns 1.2 v lvcmos 2 ma 2 ma high 5 ? 0.66 4.12 0.04 2.02 2.99 0.43 3.83 3.37 4.06 3.84 5.48 5.02 ns 1.2 v lvcmos wide range 1,3 100 a2 mahigh5?????????????ns 3.3 v pci per pci spec. ? high 10 25 4 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns 3.3 v pci-x per pci-x spec. ? high 10 25 4 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns 3.3 v gtl 20 ma 6 ? high 10 25 0.66 1.59 0.04 1.80 ? 0.43 1.56 1.59 ? ? 3.27 3.30 ns 2.5 v gtl 20 ma 6 ? high 10 25 0.66 1.63 0.04 1.75 ? 0.43 1.66 1.63 ? ? 3.37 3.34 ns 3.3 v gtl+ 35 ma ? high 10 25 0.66 1.57 0.04 1.80 ? 0.43 1.60 1.57 ? ? 3.31 3.29 ns 2.5 v gtl+ 33 ma ? high 10 25 0.66 1.69 0.04 1.75 ? 0.43 1.72 1.61 ? ? 3.43 3.32 ns hstl (i) 8 ma ? high 20 25 0.66 2.43 0.04 2.12 ? 0.43 2.48 2.41 ? ? 4.19 4.12 ns hstl (ii) 15 ma 6 ? high 20 50 0.66 2.32 0.04 2.12 ? 0.43 2.36 2.08 ? ? 4.07 3.79 ns sstl2 (i) 15 ma ? high 30 25 0.66 1.63 0.04 1.61 ? 0.43 1.66 1.41 ? ? 1.66 1.41 ns sstl2 (ii) 18 ma ? high 30 50 0.66 1. 66 0.04 1.61 ? 0.43 1.69 1.36 ? ? 1.69 1.36 ns sstl3 (i) 14 ma ? high 30 25 0.66 1.77 0.04 1.54 ? 0.43 1.80 1.41 ? ? 1.80 1.41 ns sstl3 (ii) 21 ma ? high 30 50 0.66 1. 58 0.04 1.54 ? 0.43 1.61 1.28 ? ? 1.61 1.28 ns notes: 1. the minimum drive strength for any lvcmos 1.2 v or lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jesd8-b specification. 3. all lvcmos 1.2 v software macros s upport lvcmos 1.2 v wide range as specified in the jesd8-12 specification. 4. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-12 on page 2-81 for connectivity. this resistor is not required during normal operation. 5. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. 6. output drive strength is below jedec specification.
proasic3l low power flash fpgas revision 13 2-31 lvds 24 ma ?high ??0.661.430.041.85???????? ns lvpecl 24 ma ?high ??0.661.370.041.67???????? ns table 2-33 ? summary of i/o timing character istics?software default settings ?1 speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.14 v, worst case vcci advanced i/o banks i/o standard drive strength (ma) equiv. software default drive strength option 1 slew rate capacitive load (pf) external resistor ( ? ) t dout (ns) t dp (ns) t din (ns) t py (ns) teo ut (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high 5 pf ? 0.60 1.83 0.04 0.78 0.43 1.87 1.39 2. 46 2.74 3.58 3.10 ns 3.3 v lvcmos wide range 1,2 100 a 12 ma high 5 pf ? ? ? ? ? ? ? ? ? ? ? ? ns 2.5 v lvcmos 12 ma 12 ma high 5 pf ? 0.60 1. 85 0.04 1.00 0.43 1.88 1.55 2.53 2.63 3.59 3.26 ns 1.8 v lvcmos 12 ma 12 ma high 5 pf ? 0.60 2. 04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns 1.5 v lvcmos 12 ma 12 ma high 5 pf ? 0.60 2. 33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns 1.2 v lvcmos 2 ma 2 ma high 5pf ? 0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41 ns 1.2 v lvcmos wide range 1,3 100 a 2 ma high 5 pf ? ? ? ? ? ? ? ? ? ? ? ? ns 3.3 v pci per pci spec. ? high 10 pf 25 4 0.60 2.05 0.04 0.66 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns table 2-32 ? summary of i/o timing character istics?software default settings ?1 speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.14 v, worst case vcci pro i/o banks standard drive strength (ma) equiv. software default drive strength option 1 slew rate capacitive load (pf) external resistor ( ? ) t dout (ns) t dp (ns) t din (ns) t py (ns) t pys (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units notes: 1. the minimum drive strength for any lvcmos 1.2 v or lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jesd8-b specification. 3. all lvcmos 1.2 v software macros s upport lvcmos 1.2 v wide range as specified in the jesd8-12 specification. 4. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-12 on page 2-81 for connectivity. this resistor is not required during normal operation. 5. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. 6. output drive strength is below jedec specification.
proasic3l dc and switching characteristics 2-32 revision 13 3.3 v pci-x per pci-x spec. ? high 10 pf 25 4 0.60 2.05 0.04 0.64 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns lvds 24 ma ? high ? ? 0.60 1. 40 0.04 1.23 n/a n/a n/a n/a n/a n/a n/a ns lvpecl 24 ma ? high ? ? 0.60 1.38 0.04 1.08 n/a n/a n/a n/a n/a n/a n/a ns notes: 1. the minimum drive strength for any lvcmos 1.2 v or lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jesd8-b specification. 3. all lvcmos 1.2 v software macros s upport lvcmos 1.2 v wide range as specified in the jesd8-12 specification. 4. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-12 on page 2-81 for connectivity. this resistor is not required during normal operation. 5. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-33 ? summary of i/o timing character istics?software default settings ?1 speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.14 v, worst case vcci advanced i/o banks i/o standard drive strength (ma) equiv. software default drive strength option 1 slew rate capacitive load (pf) external resistor ( ? ) t dout (ns) t dp (ns) t din (ns) t py (ns) te o ut (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units
proasic3l low power flash fpgas revision 13 2-33 detailed i/o dc characteristics table 2-34 ? summary of i/o timing character istics?software default settings ?1 speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.14 v, worst case vcci = 3.0 v standard plus i/o banks i/o standard drive strength (ma) equiv. software default drive strength option 1 slew rate capacitive load (pf) external resistor t dout (ns) t dp (ns) t din (ns) t py (ns) te o ut (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high 5 pf ? 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns 3.3 v lvcmos wide range 1,2 100 a 12 ma high 5 pf ? ? ? ? ? ? ? ? ? ? ? ? ns 2.5 v lvcmos 12 ma 12 ma high 5 pf ? 0.60 1. 59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns 1.8 v lvcmos 8 ma 8 ma high 5 pf ? 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2. 16 2.38 3.33 3.03 ns 1.5 v lvcmos 4 ma 4 ma high 5 pf ? 0.60 2.15 0.04 1.09 0.43 2.19 1.82 2. 32 2.40 3.90 3.53 ns 1.2 v lvcmos 2 ma 2 ma high 5 pf ? 0.60 3.54 0. 04 1.56 0.43 2.37 2.11 3. 60 3.87 4.02 3.76 ns 1.2 v lvcmos wide range 1,3 100 a 2 ma high 5 pf ? ? ? ? ? ? ? ? ? ? ? ? ns 3.3 v pci per pci spec. ? high 10 pf 25 4 0.60 1.77 0.04 0.65 0.43 1.80 1. 31 2.14 2.47 3.51 3.02 ns 3.3 v pci-x per pci-x spec. ? high 10 pf 25 4 0.60 1.77 0.04 0.64 0.43 1.80 1. 31 2.14 2.47 3.51 3.02 ns notes: 1. the minimum drive strength for any lvcmos 1.2 v or lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jesd8-b specification. 3. all lvcmos 1.2 v software macros s upport lvcmos 1.2 v wide range as specified in the jesd8-12 specification. 4. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-12 on page 2-81 for connectivity. this resistor is not required during normal operation. 5. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-35 ? input capacitance symbol definition conditions min. max. units c in input capacitance v in = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin v in = 0, f = 1.0 mhz 8 pf
proasic3l dc and switching characteristics 2-34 revision 13 table 2-36 ? i/o output buffer maximum resistances 1 applicable to pro i/os standard drive strength r pull-down ( ? ) 2 r pull-up ( ? ) 3 3.3 v lvttl / 3.3 v lvcmos 4 ma 100 300 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 3.3 v lvcmos wide range 100 a same as regular 3.3 v lvcmos same as regular 3.3 v lvcmos 2.5 v lvcmos 4 ma 100 200 8 ma 50 100 12 ma 25 50 16 ma 20 40 24 ma 11 22 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 12 ma 20 22 16 ma 20 22 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 1.2 v lvcmos 2 ma 158 164 1.2 v lvcmos wide range 100 a same as regular 1.2 v lvcmos same as regular 1.2 v lvcmos 3.3 v pci/pci-x per pci/pci-x specification 25 75 3.3 v gtl 20 ma 4 11 ? 2.5 v gtl 20 ma 4 14 ? 3.3 v gtl+ 35 ma 12 ? 2.5 v gtl+ 33 ma 15 ? hstl (i) 8 ma 50 50 hstl (ii) 15 ma 4 25 25 sstl2 (i) 15 ma 27 31 sstl2 (ii) 18 ma 13 15 sstl3 (i) 14 ma 44 69 sstl3 (ii) 21 ma 18 32 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on vcci, drive strength selection, temperature, and proces s. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located at http://www.microsemi.com/soc/download/ibis/default.aspx . 2. r (pull-down-max) = (volspec) / iolspec 3. r (pull-up-max) = (vccimax ? vohspec) / iohspec 4. output drive strength is below jedec specification.
proasic3l low power flash fpgas revision 13 2-35 table 2-37 ? i/o output buffer maximum resistances 1 applicable to advanced i/o banks standard drive strength r pull-down ( ? ) 2 r pull-up ( ? ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 3.3 v lvcmos wide range 100 a same as regular 3.3 v lvcmos same as regular 3.3 v lvcmos 2.5 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 1.8 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 16 ma 20 40 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 1.2 v lvcmos 2 ma 158 164 1.2 v lvcmos wide range 100 a same as regular 1.2 v lvcmos same as regular 1.2 v lvcmos 3.3 v pci/pci-x per pci/pci-x specification 25 75 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located at http://www.microsemi.com/soc/download/ibis/default.aspx . 2. r (pull-down-max) = (volspec) / iolspec 3. r (pull-up-max) = (vccimax ? vohspec) / iohspec
proasic3l dc and switching characteristics 2-36 revision 13 table 2-38 ? i/o output buffer maximum resistances 1 applicable to standard plus i/o banks standard drive strength r pull-down ( ? ) 2 r pull-up ( ? ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 25 75 3.3 v lvcmos wide range 100 a same as regular 3.3 v lvcmos same as regular 3.3 v lvcmos 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 1.2 v lvcmos 2 ma 158 164 1.2 v lvcmos wide range 100 a same as regular 1.2 v lvcmos same as regular 1.2 v lvcmos 3.3 v pci/pci-x per pci/pci-x specification 25 75 notes: 1. these maximum values are provided for informational reas ons only. minimum output buffer resistance values depend on vcci, drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located at http://www.microsemi.com/soc/download/ibis/default.aspx . 2. r (pull-down-max) = (volspec) / iolspec 3. r (pull-up-max) = (vccimax ? vohspec) / iohspec
proasic3l low power flash fpgas revision 13 2-37 table 2-39 ? i/o weak pull-up/pull-down resistances minimum and maximum weak pull-u p/pull-down resistance values vcci r (weak pull-up) 1 ( ? ) r (weak pull-down) 2 ( ? ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 3.3 v (wide range i/os) 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k 1.2 v lvcmos 25 k 110 k 25 k 150 k 1.2 v (wide range i/os) 19 k 110 k 19 k 150 k notes: 1. r (weak pull-up-max) = (vccimax ? vohspec) / i (weak pull-up-min) 2. r (weak pull-down-max) = (volspec) / i (weak pull-down-min)
proasic3l dc and switching characteristics 2-38 revision 13 table 2-40 ? i/o short currents iosh/iosl applicable to pro i/os standard drive strength iosl (ma)* iosh (ma)* 3.3 v lvttl / 3.3 v lvcmos 4 ma 25 27 8 ma 51 54 12 ma 103 109 16 ma 132 127 24 ma 268 181 3.3 v lvcmos wide range 100 a same as regular 3.3 v lvcmos same as regular 3.3 v lvcmos 2.5 v lvcmos 4 ma 16 18 8 ma 32 37 12 ma 65 74 16 ma 83 87 24 ma 169 124 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 6 ma 35 44 8 ma 45 51 12 ma 91 74 16 ma 91 74 1.5 v lvcmos 2 ma 13 16 4 ma 25 33 6 ma 32 39 8 ma 66 55 12 ma 66 55 1.2 v lvcmos 2 ma 20 26 1.2 v lvcmos wide range 100 a 20 26 3.3 v pci/pcix per pci/pci-x specification per pci curves 3.3 v gtl 20 ma 2 268 181 2.5 v gtl 20 ma 2 169 124 3.3 v gtl+ 35 ma 268 181 2.5 v gtl+ 33 ma 169 124 hstl (i) 8 ma 32 39 hstl (ii) 15 ma 2 66 55 sstl2 (i) 15 ma 83 87 sstl2 (ii) 18 ma 169 124 sstl3 (i) 14 ma 51 54 notes: 1. *tj = 100c 2. output drive strength is below jedec specification.
proasic3l low power flash fpgas revision 13 2-39 table 2-41 ? i/o short currents iosh/ios l applicable to advanced i/o banks standard drive strength iosl (ma)* iosh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 12 ma 103 109 16 ma 132 127 24 ma 268 181 3.3 v lvcmos wide range 100 a same as regular 3.3 v lvcmos same as regular 3.3 v lvcmos 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 12 ma 65 74 16 ma 83 87 24 ma 169 124 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 6 ma 35 44 8 ma 45 51 12 ma 91 74 16 ma 91 74 1.5 v lvcmos 2 ma 13 16 4 ma 25 33 6 ma 32 39 8 ma 66 55 12 ma 66 55 1.2 v lvcmos 2 ma 20 26 1.2 v lvcmos wide range 100 a 20 26 3.3 v pci/pci-x per pci/pci-x specification 103 109 note: *t j = 100c
proasic3l dc and switching characteristics 2-40 revision 13 the length of time an i/o can withstand iosh/iosl events depends on the junc tion temperature. the reliability data below is based on a 3.3 v, 12 ma i/o setting, which is the worst case for this type of analysis. for example, at 100c, the short current condition would have to be sustained for more than six months to cause a reliability concern. the i/o design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. table 2-42 ? i/o short currents iosh/iosl applicable to standard plus i/o banks drive strength iosl (ma)* iosh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 12 ma 103 109 16 ma 103 109 3.3 v lvcmos wide range 100 a same as regular 3.3 v lvcmos same as regular 3.3 v lvcmos 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 12 ma 65 74 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 6 ma 35 44 8 ma 35 44 1.5 v lvcmos 2 ma 13 16 4 ma 25 33 1.2 v lvcmos 2 ma 20 26 1.2 v lvcmos wide range 100 a 20 26 3.3 v pci/pci-x per pci/pci-x specification 103 109 note: t j = 100c table 2-43 ? schmitt trigger input hysteresis, hysteresis volt age value (typ) for schm itt mode input buffers input buffer configuration hysteresis value (typ.) 3.3 v lvttl/lvcmos/pci/pci-x (schmitt trigger mode) 240 mv 2.5 v lvcmos (schmitt trigger mode) 140 mv 1.8 v lvcmos (schmitt trigger mode) 80 mv 1.5 v lvcmos (schmitt trigger mode) 60 mv 1.2 v lvcmos (schmitt trigger mode) 40 mv
proasic3l low power flash fpgas revision 13 2-41 table 2-44 ? duration of short circuit event before failure temperature time before failure ?40c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months table 2-45 ? i/o input rise time, fall time , and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos no requirement 10 ns * 20 years (110c) lvds/b-lvds/ m-lvds/lvpecl no requirement 10 ns * 10 years (100c) note: *the maximum input rise/fall time is related to the noise induced into the input buffer trace. if the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. microsemi recommends signal integrity evaluation/char acterization of the system to ensure that there is no excessive noise coupling into input signals.
proasic3l dc and switching characteristics 2-42 revision 13 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low voltage transistor?transistor logic (lvttl) is a general-purpose standard (eia/jesd) for 3.3 v applications. this standard uses an lvttl input bu ffer and push-pull output buffer. furthermore, all lvcmos 3.3 v software macros comply with lvcmos 3.3 v wide range, as specified in the jesd8-a specification. table 2-46 ? minimum and maximum dc input and output levels applicable to pro i/o banks 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 27 25 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-47 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray.
proasic3l low power flash fpgas revision 13 2-43 table 2-48 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 103 109 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-7 ? ac loading table 2-49 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.45 note: *measuring point = vtrip. see table 2-27 on page 2-26 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
proasic3l dc and switching characteristics 2-44 revision 13 timing characteristics 1.5 v dc core voltage table 2-50 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.59 5.48 0.04 1.58 2.17 0.38 5.58 4.40 2.42 2.20 7.60 6.42 ns ?1 0.50 4.66 0.03 1.34 1.85 0.33 4.75 3.75 2.06 1.87 6.46 5.46 ns 8 ma std. 0.59 4.48 0.04 1.58 2.17 0.38 4.56 3.76 2.73 2.76 6.57 5.78 ns ?1 0.50 3.81 0.03 1.34 1.85 0.33 3.88 3.20 2.33 2.35 5.59 4.91 ns 12 ma std. 0.59 3.77 0.04 1.58 2.17 0.38 3.84 3.28 2.95 3.12 5.85 5.29 ns ?1 0.50 3.21 0.03 1.34 1.85 0.33 3.27 2.79 2.51 2.65 4.98 4.50 ns 16 ma std. 0.59 3.57 0.04 1.58 2.17 0.38 3.63 3.18 2.99 3.22 5.64 5.19 ns ?1 0.50 3.03 0.03 1.34 1.85 0.33 3.09 2.70 2.54 2.74 4.80 4.41 ns 24 ma std. 0.59 3.46 0.04 1.58 2.17 0.38 3.52 3.19 3.05 3.57 5.54 5.20 ns ?1 0.50 2.94 0.03 1.34 1.85 0.33 3.00 2.71 2.59 3.03 4.71 4.42 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-51 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.59 3.08 0.04 1.58 2.17 0.38 3.14 2.36 2.42 2.33 5.15 4.38 ns ?1 0.50 2.62 0.03 1.34 1.85 0.33 2.67 2.01 2.06 1.98 4.38 3.72 ns 8 ma std. 0.59 2.53 0.04 1.58 2.17 0.38 2.58 1.89 2.74 2.89 4.59 3.90 ns ?1 0.50 2.16 0.03 1.34 1.85 0.33 2.20 1.61 2.33 2.46 3.91 3.32 ns 12 ma std. 0.59 2.22 0.04 1.58 2.17 0.38 2.27 1.67 2.95 3.25 4.28 3.68 ns ?1 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns 16 ma std. 0.59 2.17 0.04 1.58 2.17 0.38 2.21 1.63 3.00 3.35 4.23 3.64 ns ?1 0.50 1.85 0.03 1.34 1.85 0.33 1.88 1.38 2.55 2.85 3.59 3.09 ns 24 ma std. 0.59 2.19 0.04 1.58 2.17 0.38 2.24 1.57 3.05 3.71 4.25 3.58 ns ?1 0.50 1.87 0.03 1.34 1.85 0.33 1.90 1.33 2.59 3.16 3.61 3.05 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-45 table 2-52 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.54 5.11 0.04 0.91 0. 38 5.21 4.33 2.38 2.21 7.22 6.34 ns ?1 0.46 4.35 0.03 0.78 0.33 4. 43 3.68 2.02 1.88 6.14 5.40 ns 6 ma std. 0.54 4.30 0.04 0.91 0. 38 4.38 3.75 2.68 2.74 6.39 5.76 ns ?1 0.46 3.66 0.03 0.78 0.33 3. 73 3.19 2.28 2.33 5.44 4.90 ns 8 ma std. 0.54 4.30 0.04 0.91 0. 38 4.38 3.75 2.68 2.74 6.39 5.76 ns ?1 0.46 3.66 0.03 0.78 0.33 3. 73 3.19 2.28 2.33 5.44 4.90 ns 12 ma std. 0.54 3.68 0.04 0.91 0. 38 3.75 3.32 2.89 3.07 5.76 5.33 ns ?1 0.46 3.13 0.03 0.78 0.33 3. 19 2.82 2.45 2.62 4.90 4.53 ns 16 ma std. 0.54 3.50 0.04 0.91 0. 38 3.56 3.21 2.93 3.16 5.57 5.23 ns ?1 0.46 2.97 0.03 0.78 0.33 3. 03 2.73 2.49 2.69 4.74 4.45 ns 24 ma std. 0.54 3.39 0.04 0.91 0. 38 3.45 3.25 2.99 3.50 5.47 5.26 ns ?1 0.46 2.88 0.03 0.78 0.33 2. 94 2.76 2.54 2.97 4.65 4.48 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-53 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.54 2.90 0.04 0.91 0. 38 2.96 2.28 2.38 2.35 4.97 4.29 ns ?1 0.46 2.47 0.03 0.78 0.33 2. 52 1.94 2.03 2.00 4.23 3.65 ns 6 ma std. 0.54 2.41 0.04 0.91 0. 38 2.46 1.84 2.69 2.88 4.47 3.85 ns ?1 0.46 2.05 0.03 0.78 0.33 2. 09 1.57 2.29 2.45 3.80 3.28 ns 8 ma std. 0.54 2.41 0.04 0.91 0. 38 2.46 1.84 2.69 2.88 4.47 3.85 ns ?1 0.46 2.05 0.03 0.78 0.33 2. 09 1.57 2.29 2.45 3.80 3.28 ns 12 ma std. 0.54 2.16 0.04 0.91 0.38 2.20 1.63 2.89 3.22 4.21 3.64 ns ?-1 0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns 16 ma std. 0.54 2.11 0.04 0.91 0. 38 2.15 1.59 2.94 3.31 4.17 3.61 ns ?-1 0.46 1.80 0.03 0.78 0.33 1.8 3 1.36 2.50 2.82 3.54 3.07 ns 24 ma std. 0.54 2.14 0.04 0.91 0. 38 2.17 1.55 2.99 3.65 4.19 3.56 ns ?1 0.46 1.82 0.03 0.78 0.33 1. 85 1.32 2.54 3.11 3.56 3.03 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-46 revision 13 table 2-54 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.54 4.61 0.04 0.90 0. 38 4.70 3.91 2.05 1.99 6.71 5.92 ns ?1 0.46 3.92 0.03 0.77 0.33 4. 00 3.32 1.74 1.69 5.71 5.04 ns 6 ma std. 0.54 3.80 0.04 0.90 0. 38 3.87 3.40 2.32 2.47 5.88 5.41 ns ?1 0.46 3.23 0.03 0.77 0.33 3. 29 2.89 1.98 2.10 5.00 4.60 ns 8 ma std. 0.54 3.80 0.04 0.90 0. 38 3.87 3.40 2.32 2.47 5.88 5.41 ns ?1 0.46 3.23 0.03 0.77 0.33 3. 29 2.89 1.98 2.10 5.00 4.60 ns 12 ma std. 0.54 3.22 0.04 0.90 0. 38 3.28 3.00 2.51 2.77 5.30 5.01 ns ?1 0.46 2.74 0.03 0.77 0.33 2. 79 2.55 2.14 2.36 4.51 4.27 ns 16 ma std. 0.54 3.22 0.04 0.90 0. 38 3.28 3.00 2.51 2.77 5.30 5.01 ns ?1 0.46 2.74 0.03 0.77 0.33 2. 79 2.55 2.14 2.36 4.51 4.27 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-55 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.54 2.51 0.04 0.90 0. 38 2.56 2.01 2.05 2.10 4.57 4.02 ns ?1 0.46 2.14 0.03 0.77 0.33 2. 18 1.71 1.74 1.79 3.89 3.42 ns 6 ma std. 0.54 2.05 0.04 0.90 0. 38 2.09 1.61 2.32 2.59 4.10 3.62 ns ?1 0.46 1.74 0.03 0.77 0.33 1. 78 1.37 1.97 2.20 3.49 3.08 ns 8 ma std. 0.54 2.05 0.04 0.90 0. 38 2.09 1.61 2.32 2.59 4.10 3.62 ns ?1 0.46 1.74 0.03 0.77 0.33 1. 78 1.37 1.97 2.20 3.49 3.08 ns 12 ma std. 0.54 1.83 0.04 0.90 0.38 1.86 1.41 2.51 2.90 3.88 3.42 ns ?1 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns 16 ma std. 0.54 1.83 0.04 0.90 0. 38 1.86 1.41 2.51 2.90 3.88 3.42 ns ?1 0.46 1.56 0.03 0.77 0.33 1. 59 1.20 2.14 2.47 3.30 2.91 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-47 1.2 v dc core voltage table 2-56 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.77 5.48 0.05 1.58 2.17 0. 50 5.58 4.40 2.42 2. 20 7.60 6.42 ns ?1 0.66 4.66 0.04 1.34 1.85 0.43 4. 75 3.75 2.06 1.87 6.46 5.46 ns 8 ma std. 0.77 4.48 0.05 1.58 2.17 0. 50 4.56 3.76 2.73 2. 76 6.57 5.78 ns ?1 0.66 3.81 0.04 1.34 1.85 0.43 3. 88 3.20 2.33 2.35 5.59 4.91 ns 12 ma std. 0.77 3.77 0.05 1.58 2.17 0. 50 3.84 3.28 2.95 3. 12 5.85 5.29 ns ?1 0.66 3.21 0.04 1.34 1.85 0.43 3. 27 2.79 2.51 2.65 4.98 4.50 ns 16 ma std. 0.77 3.57 0.05 1.58 2.17 0. 50 3.63 3.18 2.99 3. 22 5.64 5.19 ns ?1 0.66 3.03 0.04 1.34 1.85 0.43 3. 09 2.70 2.54 2.74 4.80 4.41 ns 24 ma std. 0.77 3.46 0.05 1.58 2.17 0. 50 3.52 3.19 3.05 3. 57 5.54 5.20 ns ?1 0.66 2.94 0.04 1.34 1.85 0.43 3. 00 2.71 2.59 3.03 4.71 4.42 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-57 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.77 3.08 0.05 1.58 2.17 0.50 3.14 2.36 2.42 2.33 5.15 4.38 ns ?1 0.66 2.62 0.04 1.34 1.85 0.43 2. 67 2.01 2.06 1.98 4.38 3.72 ns 8 ma std. 0.77 2.53 0.05 1.58 2.17 0. 50 2.58 1.89 2.74 2. 89 4.59 3.90 ns ?1 0.66 2.16 0.04 1.34 1.85 0.43 2. 20 1.61 2.33 2.46 3.91 3.32 ns 12 ma std. 0.77 2.22 0.05 1.58 2.17 0.50 2.27 1.67 2.95 3.25 4.28 3.68 ns ?1 0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns 16 ma std. 0.77 2.17 0.05 1.58 2.17 0. 50 2.21 1.63 3.00 3. 35 4.23 3.64 ns ?1 0.66 1.85 0.04 1.34 1.85 0.43 1. 88 1.38 2.55 2.85 3.59 3.09 ns 24 ma std. 0.77 2.19 0.05 1.58 2.17 0. 50 2.24 1.57 3.05 3. 71 4.25 3.58 ns ?1 0.66 1.87 0.04 1.34 1.85 0.43 1. 90 1.33 2.59 3.16 3.61 3.05 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-48 revision 13 table 2-58 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.70 5.11 0.05 0.91 0.50 5.21 4.33 2.38 2. 21 7.22 6.34 ns ?1 0.60 4.35 0.04 0.78 0.43 4.43 3.68 2.02 1.88 6.14 5.40 ns 6 ma std. 0.70 4.30 0.05 0.91 0.50 4.38 3.75 2.68 2. 74 6.39 5.76 ns ?1 0.60 3.66 0.04 0.78 0.43 3.73 3.19 2.28 2.33 5.44 4.90 ns 8 ma std. 0.70 4.30 0.05 0.91 0.50 4.38 3.75 2.68 2. 74 6.39 5.76 ns ?1 0.60 3.66 0.04 0.78 0.43 3.73 3.19 2.28 2.33 5.44 4.90 ns 12 ma std. 0.70 3.68 0.05 0.91 0.50 3.75 3.32 2.89 3. 07 5.76 5.33 ns ?1 0.60 3.13 0.04 0.78 0.43 3.19 2.82 2.45 2.62 4.90 4.53 ns 16 ma std. 0.70 3.50 0.05 0.91 0.50 3.56 3.21 2.93 3. 16 5.57 5.23 ns ?1 0.60 2.97 0.04 0.78 0.43 3.03 2.73 2.49 2.69 4.74 4.45 ns 24 ma std. 0.70 3.39 0.05 0.91 0.50 3.45 3.25 2.99 3. 50 5.47 5.26 ns ?1 0.60 2.88 0.04 0.78 0.43 2.94 2.76 2.54 2.97 4.65 4.48 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-59 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.70 2.90 0.05 0.91 0.50 2.96 2.28 2.38 2. 35 4.97 4.29 ns ?1 0.60 2.47 0.04 0.78 0.43 2.52 1.94 2.03 2.00 4.23 3.65 ns 6 ma std. 0.70 2.41 0.05 0.91 0.50 2.46 1.84 2.69 2. 88 4.47 3.85 ns ?1 0.60 2.05 0.04 0.78 0.43 2.09 1.57 2.29 2.45 3.80 3.28 ns 8 ma std. 0.70 2.41 0.05 0.91 0.50 2.46 1.84 2.69 2. 88 4.47 3.85 ns ?1 0.60 2.05 0.04 0.78 0.43 2.09 1.57 2.29 2.45 3.80 3.28 ns 12 ma std. 0.70 2.16 0.05 0.91 0.50 2.20 1.63 2.89 3.22 4.21 3.64 ns ?-1 0.60 1.83 0.04 0.78 0.43 1.87 1.39 2.46 2.74 3.58 3.10 ns 16 ma std. 0.70 2.11 0.05 0.91 0.50 2.15 1.59 2.94 3. 31 4.17 3.61 ns ?-1 0.60 1.80 0.04 0.78 0.43 1.8 3 1.36 2.50 2.82 3.54 3.07 ns 24 ma std. 0.70 2.14 0.05 0.91 0.50 2.17 1.55 2.99 3. 65 4.19 3.56 ns ?1 0.60 1.82 0.04 0.78 0.43 1.85 1.32 2.54 3.11 3.56 3.03 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-49 table 2-60 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.70 4.61 0.05 0.90 0.50 4.70 3.91 2.05 1. 99 6.71 5.92 ns ?1 0.60 3.92 0.04 0.77 0.43 4.00 3.32 1.74 1.69 5.71 5.04 ns 6 ma std. 0.70 3.80 0.05 0.90 0.50 3.87 3.40 2.32 2. 47 5.88 5.41 ns ?1 0.60 3.23 0.04 0.77 0.43 3.29 2.89 1.98 2.10 5.00 4.60 ns 8 ma std. 0.70 3.80 0.05 0.90 0.50 3.87 3.40 2.32 2. 47 5.88 5.41 ns ?1 0.60 3.23 0.04 0.77 0.43 3.29 2.89 1.98 2.10 5.00 4.60 ns 12 ma std. 0.70 3.22 0.05 0.90 0.50 3.28 3.00 2.51 2. 77 5.30 5.01 ns ?1 0.60 2.74 0.04 0.77 0.43 2.79 2.55 2.14 2.36 4.51 4.27 ns 16 ma std. 0.70 3.22 0.05 0.90 0.50 3.28 3.00 2.51 2. 77 5.30 5.01 ns ?1 0.60 2.74 0.04 0.77 0.43 2.79 2.55 2.14 2.36 4.51 4.27 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-61 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.70 2.51 0.05 0.90 0.50 2.56 2.01 2.05 2. 10 4.57 4.02 ns ?1 0.60 2.14 0.04 0.77 0.43 2.18 1.71 1.74 1.79 3.89 3.42 ns 6 ma std. 0.70 2.05 0.05 0.90 0.50 2.09 1.61 2.32 2. 59 4.10 3.62 ns ?1 0.60 1.74 0.04 0.77 0.43 1.78 1.37 1.97 2.20 3.49 3.08 ns 8 ma std. 0.70 2.05 0.05 0.90 0.50 2.09 1.61 2.32 2. 59 4.10 3.62 ns ?1 0.60 1.74 0.04 0.77 0.43 1.78 1.37 1.97 2.20 3.49 3.08 ns 12 ma std. 0.70 1.83 0.05 0.90 0.50 1.86 1.41 2.51 2.90 3.88 3.42 ns ?1 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns 16 ma std. 0.70 1.83 0.05 0.90 0.50 1.86 1.41 2.51 2. 90 3.88 3.42 ns ?1 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-50 revision 13 3.3 v lvcmos wide range table 2-62 ? minimum and maximum dc input and output levels for lvcmos 3.3 v wide range applicable to pro i/o banks 3.3 v lvcmos wide range equivalent software default drive strength option 1 vil vih vol voh iol ioh iosh iosl iil iih drive strength min. v max. v min. v max. v max. v min. vaa max. ma 2 max. ma 2 a a 100 a 2 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 25 27 10 10 100 a 4 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 25 27 10 10 100 a 6 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 51 54 10 10 100 a 8 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 51 54 10 10 100 a 12 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 103 109 10 10 100 a 16 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 132 127 10 10 100 a 24 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 268 181 10 10 notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. currents are measured at 85c junction temperature. 3. all lvmcos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jdec8-b specification 4. software default selection highlighted in gray. table 2-63 ? minimum and maximum dc input and output levels for lvcmos 3.3 v wide range applicable to advanced i/o banks 3.3 v lvcmos wide range equivalent software default drive strength option 1 vil vih vol voh iol ioh iosh iosl iil iih drive strength min. v max. v min. v max. v max. v min. vaa max. ma 2 max. ma 2 a a 100 a 2 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 25 27 10 10 100 a 4 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 25 27 10 10 100 a 6 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 51 54 10 10 100 a 8 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 51 54 10 10 100 a 12 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 51 54 10 10 100 a 16 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 103 109 10 10 100 a 24 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 132 127 10 10 notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. currents are measured at 85c junction temperature. 3. all lvmcos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jdec8-b specification 4. software default selection highlighted in gray.
proasic3l low power flash fpgas revision 13 2-51 table 2-64 ? minimum and maximum dc input and output levels for lvcmos 3.3 v wide range applicable to standard plus i/o banks 3.3 v lvcmos wide range equivalent software default drive strength option 1 vil vih vol voh iol ioh iosh iosl iil iih drive strength min. v max. v min. v max. v max. v min. vaa max. ma 2 max. ma 2 a a 100 a 2 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 25 27 10 10 100 a 4 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 25 27 10 10 100 a 6 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 51 54 10 10 100 a 8 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 51 54 10 10 100 a 12 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 103 109 10 10 100 a 16 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 103 109 10 10 notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. currents are measured at 85c junction temperature. 3. all lvmcos 3.3 v software macros s upport lvcmos 3.3 v wide range as specified in the jdec8-b specification 4. software default selection highlighted in gray.
proasic3l dc and switching characteristics 2-52 revision 13 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. table 2-65 ? minimum and maximum dc input and output levels applicable to pro i/os 2.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 4 ma ?0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10 8 ma ?0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10 12 ma ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10 16 ma ?0.3 0.7 1.7 2.7 0.7 1.7 16 16 83 87 10 10 24 ma ?0.3 0.7 1.7 2.7 0.7 1.7 24 24 169 124 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-66 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 2.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10 4 ma ?0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10 6 ma ?0.3 0.7 1.7 2.7 0.7 1.7 6 6 32 37 10 10 8 ma ?0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10 12 ma ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10 16 ma ?0.3 0.7 1.7 2.7 0.7 1.7 16 16 83 87 10 10 24 ma ?0.3 0.7 1.7 2.7 0.7 1.7 24 24 169 124 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray.
proasic3l low power flash fpgas revision 13 2-53 table 2-67 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 2.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10 4 ma ?0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10 6 ma ?0.3 0.7 1.7 2.7 0.7 1.7 6 6 32 37 10 10 8 ma ?0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10 12 ma ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-8 ? ac loading table 2-68 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.25 note: *measuring point = vtrip . see table 2-27 on page 2-26 for a complete tabl e of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
proasic3l dc and switching characteristics 2-54 revision 13 timing characteristics 1.5 v dc core voltage table 2-69 ? 2.5 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.59 6.24 0.04 1.86 2.31 0. 38 6.36 5.30 2.45 1. 98 8.37 7.31 ns ?1 0.50 5.31 0.03 1.58 1.97 0.33 5. 41 4.51 2.08 1.68 7.12 6.22 ns 8 ma std. 0.59 5.10 0.04 1.86 2.31 0. 38 5.20 4.49 2.79 2. 64 7.21 6.50 ns ?1 0.50 4.34 0.03 1.58 1.97 0.33 4. 42 3.82 2.37 2.24 6.13 5.53 ns 12 ma std. 0.59 4.29 0.04 1.86 2.31 0. 38 4.37 3.91 3.03 3. 05 6.39 5.92 ns ?1 0.50 3.65 0.03 1.58 1.97 0.33 3. 72 3.32 2.58 2.60 5.43 5.04 ns 16 ma std. 0.59 4.05 0.04 1.86 2.31 0. 38 4.12 3.78 3.08 3. 17 6.13 5.79 ns ?1 0.50 3.44 0.03 1.58 1.97 0.33 3. 51 3.22 2.62 2.70 5.22 4.93 ns 24 ma std. 0.59 3.94 0.04 1.86 2.31 0. 38 4.01 3.80 3.15 3. 60 6.03 5.81 ns ?1 0.50 3.35 0.03 1.58 1.97 0.33 3. 41 3.23 2.68 3.06 5.13 4.94 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-70 ? 2.5 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.59 3.18 0.04 1.86 2.31 0.38 3.24 2.84 2.45 2.06 5.25 4.85 ns ?1 0.50 2.71 0.03 1.58 1.97 0.33 2.76 2.42 2.08 1.75 4.47 4.13 ns 8 ma std. 0.59 2.61 0.04 1.86 2.31 0.38 2.65 2.19 2.79 2.73 4.67 4.20 ns ?1 0.50 2.22 0.03 1.58 1.97 0.33 2.26 1.86 2.37 2.32 3.97 3.57 ns 12 ma std. 0.59 2.26 0.04 1.86 2.31 0.38 2.30 1.86 3.03 3.15 4.32 3.88 ns ?1 0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns 16 ma std. 0.59 2.20 0.04 1.86 2.31 0.38 2.24 1.80 3.08 3.26 4.26 3.82 ns ?1 0.50 1.87 0.03 1.58 1.97 0.33 1.91 1.54 2.62 2.77 3.62 3.25 ns 24 ma std. 0.59 2.21 0.04 1.86 2.31 0.38 2.25 1.73 3.15 3.70 4.27 3.74 ns ?1 0.50 1.88 0.03 1.58 1.97 0.33 1.92 1.47 2.68 3.14 3.63 3.18 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-55 table 2-71 ? 2.5 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.54 5.79 0.04 1.18 0. 38 5.90 5.18 2.41 1.98 7.91 7.19 ns ?1 0.46 4.92 0.03 1.00 0.33 5. 01 4.40 2.05 1.69 6.73 6.11 ns 6 ma std. 0.54 4.84 0.04 1.18 0. 38 4.93 4.43 2.74 2.60 6.94 6.44 ns ?1 0.46 4.11 0.03 1.00 0.33 4. 19 3.77 2.33 2.21 5.90 5.48 ns 8 ma std. 0.54 4.84 0.04 1.18 0. 38 4.93 4.43 2.74 2.60 6.94 6.44 ns ?1 0.46 4.11 0.03 1.00 0.33 4. 19 3.77 2.33 2.21 5.90 5.48 ns 12 ma std. 0.54 4.13 0.04 1.18 0. 38 4.21 3.92 2.97 2.99 6.22 5.93 ns ?1 0.46 3.52 0.03 1.00 0.33 3. 58 3.33 2.53 2.54 5.29 5.04 ns 16 ma std. 0.54 3.91 0.04 1.18 0. 38 3.98 3.80 3.02 3.09 5.99 5.81 ns ?1 0.46 3.32 0.03 1.00 0.33 3. 39 3.23 2.57 2.63 5.10 4.94 ns 24 ma std. 0.54 3.85 0.04 1.18 0. 38 3.87 3.85 3.09 3.48 5.88 5.87 ns ?1 0.46 3.28 0.03 1.00 0.33 3. 29 3.28 2.63 2.96 5.01 4.99 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-72 ? 2.5 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.54 2.97 0.04 1.18 0. 38 3.03 2.74 2.41 2.07 5.04 4.75 ns ?1 0.46 2.53 0.03 1.00 0.33 2. 58 2.33 2.05 1.76 4.29 4.04 ns 6 ma std. 0.54 2.44 0.04 1.18 0. 38 2.49 2.12 2.74 2.70 4.50 4.13 ns ?1 0.46 2.08 0.03 1.00 0.33 2. 12 1.80 2.33 2.30 3.83 3.51 ns 8 ma std. 0.54 2.44 0.04 1.18 0. 38 2.49 2.12 2.74 2.70 4.50 4.13 ns ?1 0.46 2.08 0.03 1.00 0.33 2. 12 1.80 2.33 2.30 3.83 3.51 ns 12 ma std. 0.54 2.17 0.04 1.18 0.38 2.21 1.82 2.97 3.09 4.22 3.83 ns ?1 0.46 1.85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns 16 ma std. 0.54 2.12 0.04 1.18 0. 38 2.16 1.76 3.03 3.19 4.17 3.78 ns ?1 0.46 1.81 0.03 1.00 0.33 1. 84 1.50 2.57 2.72 3.55 3.21 ns 24 ma std. 0.54 2.13 0.04 1.18 0. 38 2.17 1.71 3.09 3.60 4.19 3.72 ns ?1 0.46 1.81 0.03 1.00 0.33 1. 85 1.45 2.63 3.06 3.56 3.16 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-56 revision 13 table 2-73 ? 2.5 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.54 5.27 0.04 1.17 0. 38 5.37 4.68 2.03 1.79 7.38 6.69 ns ?1 0.46 4.49 0.03 0.99 0.33 4. 57 3.98 1.73 1.52 6.28 5.69 ns 6 ma std. 0.54 4.32 0.04 1.17 0. 38 4.40 4.03 2.33 2.35 6.42 6.04 ns ?1 0.46 3.68 0.03 0.99 0.33 3. 75 3.43 1.98 2.00 5.46 5.14 ns 8 ma std. 0.54 4.32 0.04 1.17 0. 38 4.40 4.03 2.33 2.35 6.42 6.04 ns ?1 0.46 3.68 0.03 0.99 0.33 3. 75 3.43 1.98 2.00 5.46 5.14 ns 12 ma std. 0.54 3.66 0.04 1.17 0. 38 3.73 3.56 2.54 2.71 5.74 5.57 ns ?1 0.46 3.12 0.03 0.99 0.33 3. 17 3.03 2.16 2.30 4.89 4.74 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-74 ? 2.5 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.54 2.60 0.04 1.17 0. 38 2.65 2.39 2.03 1.87 4.66 4.40 ns ?1 0.46 2.21 0.03 0.99 0.33 2. 25 2.03 1.72 1.59 3.96 3.74 ns 6 ma std. 0.54 2.10 0.04 1.17 0. 38 2.14 1.83 2.33 2.44 4.16 3.84 ns ?1 0.46 1.79 0.03 0.99 0.33 1. 82 1.56 1.98 2.07 3.54 3.27 ns 8 ma std. 0.54 2.10 0.04 1.17 0. 38 2.14 1.83 2.33 2.44 4.16 3.84 ns ?1 0.46 1.79 0.03 0.99 0.33 1. 82 1.56 1.98 2.07 3.54 3.27 ns 12 ma std. 0.54 1.86 0.04 1.17 0.38 1.90 1.55 2.54 2.80 3.91 3.57 ns ?1 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-57 1.2 v dc core voltage table 2-75 ? 2.5 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.77 6.24 0.05 1.86 2.31 0. 50 6.36 5.30 2.45 1. 98 8.37 7.31 ns ?1 0.66 5.31 0.04 1.58 1.97 0.43 5. 41 4.51 2.08 1.68 7.12 6.22 ns 8 ma std. 0.77 5.10 0.05 1.86 2.31 0. 50 5.20 4.49 2.79 2. 64 7.21 6.50 ns ?1 0.66 4.34 0.04 1.58 1.97 0.43 4. 42 3.82 2.37 2.24 6.13 5.53 ns 12 ma std. 0.77 4.29 0.05 1.86 2.31 0. 50 4.37 3.91 3.03 3. 05 6.39 5.92 ns ?1 0.66 3.65 0.04 1.58 1.97 0.43 3. 72 3.32 2.58 2.60 5.43 5.04 ns 16 ma std. 0.77 4.05 0.05 1.86 2.31 0. 50 4.12 3.78 3.08 3. 17 6.13 5.79 ns ?1 0.66 3.44 0.04 1.58 1.97 0.43 3. 51 3.22 2.62 2.70 5.22 4.93 ns 24 ma std. 0.77 3.94 0.05 1.86 2.31 0. 50 4.01 3.80 3.15 3. 60 6.03 5.81 ns ?1 0.66 3.35 0.04 1.58 1.97 0.43 3. 41 3.23 2.68 3.06 5.13 4.94 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-76 ? 2.5 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.77 3.18 0.05 1.86 2.31 0. 50 3.24 2.84 2.45 2. 06 5.25 4.85 ns ?1 0.66 2.71 0.04 1.58 1.97 0.43 2. 76 2.42 2.08 1.75 4.47 4.13 ns 8 ma std. 0.77 2.61 0.05 1.86 2.31 0. 50 2.65 2.19 2.79 2. 73 4.67 4.20 ns ?1 0.66 2.22 0.04 1.58 1.97 0.43 2. 26 1.86 2.37 2.32 3.97 3.57 ns 12 ma std. 0.77 2.26 0.05 1.86 2.31 0.50 2.30 1.86 3.03 3.15 4.32 3.88 ns ?1 0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns 16 ma std. 0.77 2.20 0.05 1.86 2.31 0. 50 2.24 1.80 3.08 3. 26 4.26 3.82 ns ?1 0.66 1.87 0.04 1.58 1.97 0.43 1. 91 1.54 2.62 2.77 3.62 3.25 ns 24 ma std. 0.77 2.21 0.05 1.86 2.31 0. 50 2.25 1.73 3.15 3. 70 4.27 3.74 ns ?1 0.66 1.88 0.04 1.58 1.97 0.43 1. 92 1.47 2.68 3.14 3.63 3.18 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-58 revision 13 table 2-77 ? 2.5 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.70 5.79 0.05 1.18 0.50 5.90 5.18 2.41 1. 98 7.91 7.19 ns ?1 0.60 4.92 0.04 1.00 0.43 5.01 4.40 2.05 1.69 6.73 6.11 ns 6 ma std. 0.70 4.84 0.05 1.18 0.50 4.93 4.43 2.74 2. 60 6.94 6.44 ns ?1 0.60 4.11 0.04 1.00 0.43 4.19 3.77 2.33 2.21 5.90 5.48 ns 8 ma std. 0.70 4.84 0.05 1.18 0.50 4.93 4.43 2.74 2. 60 6.94 6.44 ns ?1 0.60 4.11 0.04 1.00 0.43 4.19 3.77 2.33 2.21 5.90 5.48 ns 12 ma std. 0.70 4.13 0.05 1.18 0.50 4.21 3.92 2.97 2. 99 6.22 5.93 ns ?1 0.60 3.52 0.04 1.00 0.43 3.58 3.33 2.53 2.54 5.29 5.04 ns 16 ma std. 0.70 3.91 0.05 1.18 0.50 3.98 3.80 3.02 3. 09 5.99 5.81 ns ?1 0.60 3.32 0.04 1.00 0.43 3.39 3.23 2.57 2.63 5.10 4.94 ns 24 ma std. 0.70 3.85 0.05 1.18 0.50 3.87 3.85 3.09 3. 48 5.88 5.87 ns ?1 0.60 3.28 0.04 1.00 0.43 3.29 3.28 2.63 2.96 5.01 4.99 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-78 ? 2.5 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.70 2.97 0.05 1.18 0.50 3.03 2.74 2.41 2. 07 5.04 4.75 ns ?1 0.60 2.53 0.04 1.00 0.43 2.58 2.33 2.05 1.76 4.29 4.04 ns 6 ma std. 0.70 2.44 0.05 1.18 0.50 2.49 2.12 2.74 2. 70 4.50 4.13 ns ?1 0.60 2.08 0.04 1.00 0.43 2.12 1.80 2.33 2.30 3.83 3.51 ns 8 ma std. 0.70 2.44 0.05 1.18 0.50 2.49 2.12 2.74 2. 70 4.50 4.13 ns ?1 0.60 2.08 0.04 1.00 0.43 2.12 1.80 2.33 2.30 3.83 3.51 ns 12 ma std. 0.70 2.17 0.05 1.18 0.50 2.21 1.82 2.97 3.09 4.22 3.83 ns ?1 0.60 1.85 0.04 1.00 0.43 1.88 1.55 2.53 2.63 3.59 3.26 ns 16 ma std. 0.70 2.12 0.05 1.18 0.50 2.16 1.76 3.03 3. 19 4.17 3.78 ns ?1 0.60 1.81 0.04 1.00 0.43 1.84 1.50 2.57 2.72 3.55 3.21 ns 24 ma std. 0.70 2.13 0.05 1.18 0.50 2.17 1.71 3.09 3. 60 4.19 3.72 ns ?1 0.60 1.81 0.04 1.00 0.43 1.85 1.45 2.63 3.06 3.56 3.16 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-59 table 2-79 ? 2.5 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v applicable to standard plus i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.70 5.27 0.05 1.17 0.50 5.37 4.68 2.03 1. 79 7.38 6.69 ns ?1 0.60 4.49 0.04 0.99 0.43 4.57 3.98 1.73 1.52 6.28 5.69 ns 6 ma std. 0.70 4.32 0.05 1.17 0.50 4.40 4.03 2.33 2. 35 6.42 6.04 ns ?1 0.60 3.68 0.04 0.99 0.43 3.75 3.43 1.98 2.00 5.46 5.14 ns 8 ma std. 0.70 4.32 0.05 1.17 0.50 4.40 4.03 2.33 2. 35 6.42 6.04 ns ?1 0.60 3.68 0.04 0.99 0.43 3.75 3.43 1.98 2.00 5.46 5.14 ns 12 ma std. 0.70 3.66 0.05 1.17 0.50 3.73 3.56 2.54 2. 71 5.74 5.57 ns ?1 0.60 3.12 0.04 0.99 0.43 3.17 3.03 2.16 2.30 4.89 4.74 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-80 ? 2.5 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v applicable to standard plus i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.70 2.60 0.05 1.17 0.50 2.65 2.39 2.03 1. 87 4.66 4.40 ns ?1 0.60 2.21 0.04 0.99 0.43 2.25 2.03 1.72 1.59 3.96 3.74 ns 6 ma std. 0.70 2.10 0.05 1.17 0.50 2.14 1.83 2.33 2. 44 4.16 3.84 ns ?1 0.60 1.79 0.04 0.99 0.43 1.82 1.56 1.98 2.07 3.54 3.27 ns 8 ma std. 0.70 2.10 0.05 1.17 0.50 2.14 1.83 2.33 2. 44 4.16 3.84 ns ?1 0.60 1.79 0.04 0.99 0.43 1.82 1.56 1.98 2.07 3.54 3.27 ns 12 ma std. 0.70 1.86 0.05 1.17 0.50 1.90 1.55 2.54 2.80 3.91 3.57 ns ?1 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-60 revision 13 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standa rd (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 2-81 ? minimum and maximum dc input and output levels applicable to pro i/os 1.8 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. vmin. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1. 9 0.45 vcci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 1. 9 0.45 vcci ? 0.45 4 4 17 22 10 10 6 ma ?0.3 0.35 * vcci 0.65 * vcci 1. 9 0.45 vcci ? 0.45 6 6 35 44 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 1. 9 0.45 vcci ? 0.45 8 8 45 51 10 10 12 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 12 12 91 74 10 10 16 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 16 16 91 74 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-82 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 1.8 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1. 9 0.45 vcci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 4 4 17 22 10 10 6 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 6 6 35 44 10 10 8 ma ?0.3 0.35 * vcci 0.65 * v cci 1.9 0.45 vcci ? 0.45 8 8 45 51 10 10 12 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 12 12 91 74 10 10 16 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 16 16 91 74 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray.
proasic3l low power flash fpgas revision 13 2-61 table 2-83 ? minimum and maximum dc input and output levels applicable to standard plus i/o i/o banks 1.8 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 4 4 17 22 10 10 6 ma ?0.3 0.35 * vcci 0.65 * v cci 1.9 0.45 vcci ? 0.45 6 6 35 44 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 8 8 35 44 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-9 ? ac loading table 2-84 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.95 note: *measuring point = v trip. see table 2-27 on page 2-26 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
proasic3l dc and switching characteristics 2-62 revision 13 timing characteristics 1.5 v dc core voltage table 2-85 ? 1.8 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.59 8.32 0.04 1.80 2.55 0. 38 8.48 6.99 2.50 1.42 10.49 9.00 ns ?1 0.50 7.08 0.03 1.53 2.17 0.33 7.21 5.95 2.13 1.21 8.92 7.66 ns 4 ma std. 0.59 6.85 0.04 1.80 2.55 0. 38 6.98 5.89 2.93 2.50 8.99 7.90 ns ?1 0.50 5.83 0.03 1.53 2.17 0.33 5.94 5.01 2.49 2.12 7.65 6.72 ns 6 ma std. 0.59 5.81 0.04 1.80 2.55 0. 38 5.92 5.13 3.21 3.02 7.93 7.15 ns ?1 0.50 4.94 0.03 1.53 2.17 0.33 5.03 4.37 2.73 2.57 6.75 6.08 ns 8 ma std. 0.59 5.46 0.04 1.80 2.55 0. 38 5.56 4.99 3.28 3.17 7.57 7.00 ns ?1 0.50 4.64 0.03 1.53 2.17 0.33 4.73 4.24 2.79 2.70 6.44 5.95 ns 12 ma std. 0.59 5.36 0.04 1.80 2.55 0. 38 5.46 4.99 3.37 3.70 7.47 7.01 ns ?1 0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35 5.96 ns 16 ma std. 0.59 5.36 0.04 1.80 2.55 0. 38 5.46 4.99 3.37 3.70 7.47 7.01 ns ?1 0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35 5.96 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-86 ? 1.8 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.59 3.76 0.04 1.80 2.55 0. 38 3.83 3.68 2.50 1.47 5.84 5.70 ns ?1 0.50 3.20 0.03 1.53 2.17 0.33 3.26 3.13 2.13 1.25 4.97 4.85 ns 4 ma std. 0.59 3.05 0.04 1.80 2.55 0. 38 3.11 2.73 2.92 2.58 5.12 4.75 ns ?1 0.50 2.59 0.03 1.53 2.17 0.33 2.64 2.33 2.49 2.19 4.35 4.04 ns 6 ma std. 0.59 2.61 0.04 1.80 2.55 0. 38 2.66 2.27 3.21 3.12 4.67 4.28 ns ?1 0.50 2.22 0.03 1.53 2.17 0.33 2.26 1.93 2.73 2.65 3.98 3.64 ns 8 ma std. 0.59 2.53 0.04 1.80 2.55 0. 38 2.58 2.18 3.27 3.26 4.59 4.19 ns ?1 0.50 2.15 0.03 1.53 2.17 0.33 2.19 1.85 2.78 2.77 3.90 3.57 ns 12 ma std. 0.59 2.52 0.04 1.80 2.55 0.38 2.56 2.07 3.36 3.81 4.58 4.08 ns ?1 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns 16 ma std. 0.59 2.52 0.04 1.80 2.55 0. 38 2.56 2.07 3.36 3.81 4.58 4.08 ns ?1 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-63 table 2-87 ? 1.8 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.54 7.77 0.04 1.18 0. 38 7.92 6.80 2.50 1.44 9.93 8.81 ns ?1 0.46 6.61 0.03 1.00 0.33 6. 73 5.78 2.13 1.22 8.45 7.49 ns 4 ma std. 0.54 6.38 0.04 1.18 0. 38 6.50 5.78 2.91 2.46 8.51 7.79 ns ?1 0.46 5.43 0.03 1.00 0.33 5. 53 4.91 2.47 2.09 7.24 6.63 ns 6 ma std. 0.54 5.48 0.04 1.18 0. 38 5.58 5.11 3.18 2.94 7.59 7.12 ns ?1 0.46 4.66 0.03 1.00 0.33 4. 75 4.35 2.71 2.51 6.46 6.06 ns 8 ma std. 0.54 5.17 0.04 1.18 0. 38 5.26 4.97 3.24 3.07 7.27 6.98 ns ?1 0.46 4.40 0.03 1.00 0.33 4. 48 4.23 2.76 2.61 6.19 5.94 ns 12 ma std. 0.54 5.06 0.04 1.18 0. 38 5.15 5.03 3.34 3.55 7.17 7.04 ns ?1 0.46 4.30 0.03 1.00 0.33 4. 38 4.28 2.84 3.02 6.10 5.99 ns 16 ma std. 0.54 5.06 0.04 1.18 0. 38 5.15 5.03 3.34 3.55 7.17 7.04 ns ?1 0.46 4.30 0.03 1.00 0.33 4. 38 4.28 2.84 3.02 6.10 5.99 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-88 ? 1.8 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.54 3.60 0.04 1.10 0. 38 3.66 3.52 2.49 1.49 5.68 5.53 ns ?1 0.46 3.06 0.03 0.93 0.33 3. 12 3.00 2.12 1.27 4.83 4.71 ns 4 ma std. 0.54 2.81 0.04 1.10 0. 38 2.87 2.64 2.90 2.55 4.88 4.65 ns ?1 0.46 2.39 0.03 0.93 0.33 2. 44 2.25 2.47 2.17 4.15 3.96 ns 6 ma std. 0.54 2.47 0.04 1.10 0. 38 2.51 2.21 3.18 3.04 4.53 4.22 ns ?1 0.46 2.10 0.03 0.93 0.33 2. 14 1.88 2.70 2.59 3.85 3.59 ns 8 ma std. 0.54 2.40 0.04 1.10 0.38 2.45 2.13 3.24 3.17 4.46 4.14 ns ?1 0.46 2.04 0.03 0.93 0.33 2.08 1.81 2.76 2.70 3.79 3.52 ns 12 ma std. 0.54 2.39 0.04 1.10 0. 38 2.44 2.04 3.33 3.67 4.45 4.05 ns ?1 0.46 2.04 0.03 0.93 0.33 2. 08 1.73 2.83 3.12 3.79 3.45 ns 16 ma std. 0.54 2.39 0.04 1.10 0. 38 2.44 2.04 3.33 3.67 4.45 4.05 ns ?1 0.46 2.04 0.03 0.93 0.33 2. 08 1.73 2.83 3.12 3.79 3.45 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-64 revision 13 table 2-89 ? 1.8 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.54 7.21 0.04 1.17 0. 38 7.35 6.14 2.03 1.32 9.36 8.16 ns ?1 0.46 6.13 0.03 0.99 0.33 6. 25 5.23 1.72 1.12 7.96 6.94 ns 4 ma std. 0.54 5.81 0.04 1.17 0. 38 5.92 5.26 2.39 2.25 7.93 7.27 ns ?1 0.46 4.94 0.03 0.99 0.33 5. 03 4.47 2.03 1.91 6.74 6.19 ns 6 ma std. 0.54 4.96 0.04 1.17 0. 38 5.05 4.65 2.64 2.69 7.06 6.66 ns ?1 0.46 4.22 0.03 0.99 0.33 4. 30 3.96 2.25 2.29 6.01 5.67 ns 8 ma std. 0.54 4.96 0.04 1.17 0. 38 5.05 4.65 2.64 2.69 7.06 6.66 ns ?1 0.46 4.22 0.03 0.99 0.33 4. 30 3.96 2.25 2.29 6.01 5.67 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-90 ? 1.8 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.54 3.22 0.04 1.08 0. 38 3.28 3.04 2.02 1.37 5.30 5.06 ns ?1 0.46 2.74 0.03 0.92 0.33 2. 79 2.59 1.72 1.17 4.50 4.30 ns 4 ma std. 0.54 2.48 0.04 1.08 0. 38 2.53 2.25 2.38 2.34 4.54 4.26 ns ?1 0.46 2.11 0.03 0.92 0.33 2. 15 1.92 2.03 1.99 3.86 3.63 ns 6 ma std. 0.54 2.17 0.04 1.08 0. 38 2.21 1.86 2.64 2.79 4.22 3.87 ns ?1 0.46 1.85 0.03 0.92 0.33 1. 88 1.58 2.24 2.37 3.59 3.29 ns 8 ma std. 0.54 2.17 0.04 1.08 0.38 2.21 1.86 2.64 2.79 4.22 3.87 ns ?1 0.46 1.85 0.03 0.92 0.33 1.88 1.58 2.24 2.37 3.59 3.29 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-65 1.2 v dc core voltage table 2-91 ? 1.8 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.77 8.32 0.05 1.80 2.55 0. 50 8.48 6.99 2.50 1.42 10.49 9.00 ns ?1 0.66 7.08 0.04 1.53 2.17 0.43 7. 21 5.95 2.13 1.21 8.92 7.66 ns 4 ma std. 0.77 6.85 0.05 1.80 2.55 0. 50 6.98 5.89 2.93 2. 50 8.99 7.90 ns ?1 0.66 5.83 0.04 1.53 2.17 0.43 5. 94 5.01 2.49 2.12 7.65 6.72 ns 6 ma std. 0.77 5.81 0.05 1.80 2.55 0. 50 5.92 5.13 3.21 3. 02 7.93 7.15 ns ?1 0.66 4.94 0.04 1.53 2.17 0.43 5. 03 4.37 2.73 2.57 6.75 6.08 ns 8 ma std. 0.77 5.46 0.05 1.80 2.55 0. 50 5.56 4.99 3.28 3. 17 7.57 7.00 ns ?1 0.66 4.64 0.04 1.53 2.17 0.43 4. 73 4.24 2.79 2.70 6.44 5.95 ns 12 ma std. 0.77 5.36 0.05 1.80 2.55 0. 50 5.46 4.99 3.37 3.70 7.47 7.01 ns ?1 0.66 4.56 0.04 1.53 2.17 0.43 4.64 4.25 2.86 3.14 6.35 5.96 ns 16 ma std. 0.77 5.36 0.05 1.80 2.55 0. 50 5.46 4.99 3.37 3. 70 7.47 7.01 ns ?1 0.66 4.56 0.04 1.53 2.17 0.43 4. 64 4.25 2.86 3.14 6.35 5.96 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-92 ? 1.8 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.77 3.76 0.05 1.80 2.55 0. 50 3.83 3.68 2.50 1. 47 5.84 5.70 ns ?1 0.66 3.20 0.04 1.53 2.17 0.43 3. 26 3.13 2.13 1.25 4.97 4.85 ns 4 ma std. 0.77 3.05 0.05 1.80 2.55 0. 50 3.11 2.73 2.92 2.58 5.12 4.75 ns ?1 0.66 2.59 0.04 1.53 2.17 0.43 2. 64 2.33 2.49 2.19 4.35 4.04 ns 6 ma std. 0.77 2.61 0.05 1.80 2.55 0. 50 2.66 2.27 3.21 3. 12 4.67 4.28 ns ?1 0.66 2.22 0.04 1.53 2.17 0.43 2. 26 1.93 2.73 2.65 3.98 3.64 ns 8 ma std. 0.77 2.53 0.05 1.80 2.55 0. 50 2.58 2.18 3.27 3. 26 4.59 4.19 ns ?1 0.66 2.15 0.04 1.53 2.17 0.43 2. 19 1.85 2.78 2.77 3.90 3.57 ns 12 ma std. 0.77 2.52 0.05 1.80 2.55 0.50 2.56 2.07 3.36 3.81 4.58 4.08 ns ?1 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns 16 ma std. 0.77 2.52 0.05 1.80 2.55 0. 50 2.56 2.07 3.36 3. 81 4.58 4.08 ns ?1 0.66 2.14 0.04 1.53 2.17 0.43 2. 18 1.76 2.86 3.24 3.89 3.47 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-66 revision 13 table 2-93 ? 1.8 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 7.77 0.05 1.18 0.50 7.92 6.80 2.50 1. 44 9.93 8.81 ns ?1 0.60 6.61 0.04 1.00 0.43 6.73 5.78 2.13 1.22 8.45 7.49 ns 4 ma std. 0.70 6.38 0.05 1.18 0.50 6.50 5.78 2.91 2. 46 8.51 7.79 ns ?1 0.60 5.43 0.04 1.00 0.43 5.53 4.91 2.47 2.09 7.24 6.63 ns 6 ma std. 0.70 5.48 0.05 1.18 0.50 5.58 5.11 3.18 2. 94 7.59 7.12 ns ?1 0.60 4.66 0.04 1.00 0.43 4.75 4.35 2.71 2.51 6.46 6.06 ns 8 ma std. 0.70 5.17 0.05 1.18 0.50 5.26 4.97 3.24 3. 07 7.27 6.98 ns ?1 0.60 4.40 0.04 1.00 0.43 4.48 4.23 2.76 2.61 6.19 5.94 ns 12 ma std. 0.70 5.06 0.05 1.18 0.50 5.15 5.03 3.34 3. 55 7.17 7.04 ns ?1 0.60 4.30 0.04 1.00 0.43 4.38 4.28 2.84 3.02 6.10 5.99 ns 16 ma std. 0.70 5.06 0.05 1.18 0.50 5.15 5.03 3.34 3. 55 7.17 7.04 ns ?1 0.60 4.30 0.04 1.00 0.43 4.38 4.28 2.84 3.02 6.10 5.99 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-94 ? 1.8 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 3.60 0.05 1.10 0.50 3.66 3.52 2.49 1. 49 5.68 5.53 ns ?1 0.60 3.06 0.04 0.93 0.43 3.12 3.00 2.12 1.27 4.83 4.71 ns 4 ma std. 0.70 2.81 0.05 1.10 0.50 2.87 2.64 2.90 2. 55 4.88 4.65 ns ?1 0.60 2.39 0.04 0.93 0.43 2.44 2.25 2.47 2.17 4.15 3.96 ns 6 ma std. 0.70 2.47 0.05 1.10 0.50 2.51 2.21 3.18 3. 04 4.53 4.22 ns ?1 0.60 2.10 0.04 0.93 0.43 2.14 1.88 2.70 2.59 3.85 3.59 ns 8 ma std. 0.70 2.40 0.05 1.10 0.50 2.45 2.13 3.24 3.17 4.46 4.14 ns ?1 0.60 2.04 0.04 0.93 0.43 2.08 1.81 2.76 2.70 3.79 3.52 ns 12 ma std. 0.70 2.39 0.05 1.10 0.50 2.44 2.04 3.33 3. 67 4.45 4.05 ns ?1 0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns 16 ma std. 0.70 2.39 0.05 1.10 0.50 2.44 2.04 3.33 3. 67 4.45 4.05 ns ?1 0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-67 table 2-95 ? 1.8 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 7.21 0.05 1.17 0.50 7.35 6.14 2.03 1. 32 9.36 8.16 ns ?1 0.60 6.13 0.04 0.99 0.43 6.25 5.23 1.72 1.12 7.96 6.94 ns 4 ma std. 0.70 5.81 0.05 1.17 0.50 5.92 5.26 2.39 2. 25 7.93 7.27 ns ?1 0.60 4.94 0.04 0.99 0.43 5.03 4.47 2.03 1.91 6.74 6.19 ns 6 ma std. 0.70 4.96 0.05 1.17 0.50 5.05 4.65 2.64 2. 69 7.06 6.66 ns ?1 0.60 4.22 0.04 0.99 0.43 4.30 3.96 2.25 2.29 6.01 5.67 ns 8 ma std. 0.70 4.96 0.05 1.17 0.50 5.05 4.65 2.64 2. 69 7.06 6.66 ns ?1 0.60 4.22 0.04 0.99 0.43 4.30 3.96 2.25 2.29 6.01 5.67 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-96 ? 1.8 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 3.22 0.05 1.08 0.50 3.28 3.04 2.02 1. 37 5.30 5.06 ns ?1 0.60 2.74 0.04 0.92 0.43 2.79 2.59 1.72 1.17 4.50 4.30 ns 4 ma std. 0.70 2.48 0.05 1.08 0.50 2.53 2.25 2.38 2. 34 4.54 4.26 ns ?1 0.60 2.11 0.04 0.92 0.43 2.15 1.92 2.03 1.99 3.86 3.63 ns 6 ma std. 0.70 2.17 0.05 1.08 0.50 2.21 1.86 2.64 2. 79 4.22 3.87 ns ?1 0.60 1.85 0.04 0.92 0.43 1.88 1.58 2.24 2.37 3.59 3.29 ns 8 ma std. 0.70 2.17 0.05 1.08 0.50 2.21 1.86 2.64 2.79 4.22 3.87 ns ?1 0.60 1.85 0.04 0.92 0.43 1.88 1.58 2.24 2.37 3.59 3.29 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-68 revision 13 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 2-97 ? minimum and maximum dc input and output levels applicable to pro i/os 1.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 2 2 13 16 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 4 4 25 33 10 10 6 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 6 6 32 39 10 10 8 ma ?0.3 0.35 * vcci 0.65 * v cci 1.575 0.25 * vcci 0.75 * v cci 8 8 66 55 10 10 12 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 12 12 66 55 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-98 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 1.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 2 2 13 16 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 4 4 25 33 10 10 6 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 6 6 32 39 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 8 8 66 55 10 10 12 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 12 12 66 55 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray.
proasic3l low power flash fpgas revision 13 2-69 table 2-99 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 1.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 2 2 13 16 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 4 4 25 33 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-10 ? ac loading table 2-100 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.50.755 note: *measuring point = vtrip. see table 2-27 on page 2-26 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
proasic3l dc and switching characteristics 2-70 revision 13 timing characteristics 1.5 v dc core voltage table 2-101 ? 1.5 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.59 8.65 0.04 1.99 2.77 0. 38 8.81 7.17 3.06 2.41 10.83 9.18 ns ?1 0.50 7.36 0.03 1.69 2.36 0.33 7.50 6.10 2.61 2.05 9.21 7.81 ns 4 ma std. 0.59 7.40 0.04 1.99 2.77 0.38 7.53 6.26 3.39 3.02 9.55 8.27 ns ?1 0.50 6.29 0.03 1.69 2.36 0.33 6.41 5.33 2.89 2.57 8.12 7.04 ns 6 ma std. 0.59 6.94 0.04 1.99 2.77 0.38 7.07 6.09 3.46 3.19 9.08 8.11 ns ?1 0.50 5.91 0.03 1.69 2.36 0.33 6.01 5.18 2.94 2.72 7.73 6.90 ns 8 ma std. 0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99 8.11 ns ?1 0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65 6.90 ns 12 ma std. 0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99 8.11 ns ?1 0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65 6.90 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-102 ? 1.5 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.59 3.55 0.04 1.99 2.77 0.38 3.62 3.22 3.05 2.51 5.63 5.23 ns ?1 0.50 3.02 0.03 1.69 2.36 0.33 3.08 2.74 2.60 2.14 4.79 4.45 ns 4 ma std. 0.59 3.03 0.04 1.99 2.77 0.38 3.08 2.64 3.38 3.13 5.10 4.65 ns ?1 0.50 2.58 0.03 1.69 2.36 0.33 2.62 2.25 2.87 2.66 4.34 3.96 ns 6 ma std. 0.59 2.93 0.04 1.99 2.77 0.38 2.98 2.53 3.45 3.30 4.99 4.54 ns ?1 0.50 2.49 0.03 1.69 2.36 0.33 2.54 2.15 2.93 2.81 4.25 3.86 ns 8 ma std. 0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96 4.41 ns ?1 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns 12 ma std. 0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96 4.41 ns ?1 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-71 table 2-103 ? 1.5 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.54 8.00 0.04 1.18 0.38 8.15 7.01 3.06 2.38 10.16 9.02 ns ?1 0.46 6.80 0.03 1.00 0.33 6. 93 5.96 2.60 2.02 8.64 7.68 ns 4 ma std. 0.54 6.91 0.04 1.18 0. 38 7.04 6.21 3.37 2.94 9.05 8.22 ns ?1 0.46 5.88 0.03 1.00 0.33 5. 99 5.28 2.87 2.50 7.70 7.00 ns 6 ma std. 0.54 6.51 0.04 1.18 0. 38 6.63 6.05 3.45 3.09 8.64 8.06 ns ?1 0.46 5.54 0.03 1.00 0.33 5. 64 5.15 2.93 2.63 7.35 6.86 ns 8 ma std. 0.54 6.41 0.04 1.18 0. 38 6.53 6.11 3.56 3.64 8.54 8.12 ns ?1 0.46 5.45 0.03 1.00 0.33 5. 56 5.20 3.03 3.10 7.27 6.91 ns 12 ma std. 0.54 6.41 0.04 1.18 0. 38 6.53 6.11 3.56 3.64 8.54 8.12 ns ?1 0.46 5.45 0.03 1.00 0.33 5. 56 5.20 3.03 3.10 7.27 6.91 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-104 ? 1.5 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.54 3.60 0.04 1.10 0. 38 3.66 3.52 2.49 1.49 5.68 5.53 ns ?1 0.46 3.06 0.03 0.93 0.33 3. 12 3.00 2.12 1.27 4.83 4.71 ns 4 ma std. 0.54 2.81 0.04 1.10 0. 38 2.87 2.64 2.90 2.55 4.88 4.65 ns ?1 0.46 2.39 0.03 0.93 0.33 2. 44 2.25 2.47 2.17 4.15 3.96 ns 6 ma std. 0.54 2.47 0.04 1.10 0. 38 2.51 2.21 3.18 3.04 4.53 4.22 ns ?1 0.46 2.10 0.03 0.93 0.33 2. 14 1.88 2.70 2.59 3.85 3.59 ns 8 ma std. 0.54 2.40 0.04 1.10 0.38 2.45 2.13 3.24 3.17 4.46 4.14 ns ?1 0.46 2.04 0.03 0.93 0.33 2.08 1.81 2.76 2.70 3.79 3.52 ns 12 ma std. 0.54 2.39 0.04 1.10 0. 38 2.44 2.04 3.33 3.67 4.45 4.05 ns ?1 0.46 2.04 0.03 0.93 0.33 2. 08 1.73 2.83 3.12 3.79 3.45 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-72 revision 13 table 2-105 ? 1.5 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.54 7.32 0.04 1.17 0. 38 7.45 6.38 2.44 2.18 9.46 8.40 ns ?1 0.46 6.22 0.03 0.99 0.33 6. 34 5.43 2.08 1.86 8.05 7.14 ns 4 ma std. 0.54 6.29 0.04 1.17 0. 38 6.40 5.65 2.73 2.70 8.42 7.67 ns ?1 0.46 5.35 0.03 0.99 0.33 5. 45 4.81 2.33 2.29 7.16 6.52 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-106 ? 1.5 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.54 2.90 0.04 1.28 0. 38 2.95 2.63 2.44 2.29 4.97 4.64 ns ?1 0.46 2.47 0.03 1.09 0.33 2. 51 2.24 2.07 1.95 4.23 3.95 ns 4 ma std. 0.54 2.52 0.04 1.28 0.38 2.57 2.14 2.73 2.82 4.58 4.15 ns ?1 0.46 2.15 0.03 1.09 0.33 2.19 1.82 2.32 2.40 3.90 3.53 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-73 1.2 v dc core voltage table 2-107 ? 1.5 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.77 8.65 0.05 1.99 2.77 0. 50 8.81 7.17 3.06 2.41 10.83 9.18 ns ?1 0.66 7.36 0.04 1.69 2.36 0.43 7. 50 6.10 2.61 2.05 9.21 7.81 ns 4 ma std. 0.77 7.40 0.05 1.99 2.77 0. 50 7.53 6.26 3.39 3. 02 9.55 8.27 ns ?1 0.66 6.29 0.04 1.69 2.36 0.43 6. 41 5.33 2.89 2.57 8.12 7.04 ns 6 ma std. 0.77 6.94 0.05 1.99 2.77 0. 50 7.07 6.09 3.46 3. 19 9.08 8.11 ns ?1 0.66 5.91 0.04 1.69 2.36 0.43 6. 01 5.18 2.94 2.72 7.73 6.90 ns 8 ma std. 0.77 6.85 0.05 1.99 2.77 0. 50 6.98 6.10 3.57 3. 80 8.99 8.11 ns ?1 0.66 5.83 0.04 1.69 2.36 0.43 5. 94 5.19 3.04 3.23 7.65 6.90 ns 12 ma std. 0.77 6.85 0.05 1.99 2.77 0.50 6.98 6.10 3.57 3.80 8.99 8.11 ns ?1 0.66 5.83 0.04 1.69 2.36 0.43 5.94 5.19 3.04 3.23 7.65 6.90 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-108 ? 1.5 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.77 3.55 0.05 1.99 2.77 0. 50 3.62 3.22 3.05 2. 51 5.63 5.23 ns ?1 0.66 3.02 0.04 1.69 2.36 0.43 3. 08 2.74 2.60 2.14 4.79 4.45 ns 4 ma std. 0.77 3.03 0.05 1.99 2.77 0. 50 3.08 2.64 3.38 3. 13 5.10 4.65 ns ?1 0.66 2.58 0.04 1.69 2.36 0.43 2. 62 2.25 2.87 2.66 4.34 3.96 ns 6 ma std. 0.77 2.93 0.05 1.99 2.77 0. 50 2.98 2.53 3.45 3. 30 4.99 4.54 ns ?1 0.66 2.49 0.04 1.69 2.36 0.43 2. 54 2.15 2.93 2.81 4.25 3.86 ns 8 ma std. 0.77 2.90 0.05 1.99 2.77 0. 50 2.95 2.39 3.57 3. 94 4.96 4.41 ns ?1 0.66 2.46 0.04 1.69 2.36 0.43 2. 51 2.04 3.03 3.35 4.22 3.75 ns 12 ma std. 0.77 2.90 0.05 1.99 2.77 0.50 2.95 2.39 3.57 3.94 4.96 4.41 ns ?1 0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-74 revision 13 table 2-109 ? 1.5 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 8.00 0.05 1.18 0.50 8.15 7.01 3.06 2.38 10.16 9.02 ns ?1 0.60 6.80 0.04 1.00 0.43 6.93 5.96 2.60 2.02 8.64 7.68 ns 4 ma std. 0.70 6.91 0.05 1.18 0.50 7.04 6.21 3.37 2. 94 9.05 8.22 ns ?1 0.60 5.88 0.04 1.00 0.43 5.99 5.28 2.87 2.50 7.70 7.00 ns 6 ma std. 0.70 6.51 0.05 1.18 0.50 6.63 6.05 3.45 3. 09 8.64 8.06 ns ?1 0.60 5.54 0.04 1.00 0.43 5.64 5.15 2.93 2.63 7.35 6.86 ns 8 ma std. 0.70 6.41 0.05 1.18 0.50 6.53 6.11 3.56 3. 64 8.54 8.12 ns ?1 0.60 5.45 0.04 1.00 0.43 5.56 5.20 3.03 3.10 7.27 6.91 ns 12 ma std. 0.70 6.41 0.05 1.18 0.50 6.53 6.11 3.56 3. 64 8.54 8.12 ns ?1 0.60 5.45 0.04 1.00 0.43 5.56 5.20 3.03 3.10 7.27 6.91 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-110 ? 1.5 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 3.26 0.05 1.30 0.50 3.32 3.11 3.05 2. 49 5.33 5.12 ns ?1 0.60 2.77 0.04 1.10 0.43 2.82 2.64 2.59 2.12 4.53 4.36 ns 4 ma std. 0.70 2.84 0.05 1.30 0.50 2.89 2.57 3.37 3. 06 4.90 4.59 ns ?1 0.60 2.41 0.04 1.10 0.43 2.46 2.19 2.86 2.60 4.17 3.90 ns 6 ma std. 0.70 2.76 0.05 1.30 0.50 2.81 2.47 3.44 3. 21 4.82 4.48 ns ?1 0.60 2.35 0.04 1.10 0.43 2.39 2.10 2.92 2.73 4.10 3.81 ns 8 ma std. 0.70 2.74 0.05 1.30 0.50 2.79 2.36 3.55 3.78 4.80 4.37 ns ?1 0.60 2.33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns 12 ma std. 0.70 2.74 0.05 1.30 0.50 2.79 2.36 3.55 3. 78 4.80 4.37 ns ?1 0.60 2.33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-75 table 2-111 ? 1.5 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 7.32 0.05 1.17 0.50 7.45 6.38 2.44 2. 18 9.46 8.40 ns ?1 0.60 6.22 0.04 0.99 0.43 6.34 5.43 2.08 1.86 8.05 7.14 ns 4 ma std. 0.70 6.29 0.05 1.17 0.50 6.40 5.65 2.73 2. 70 8.42 7.67 ns ?1 0.60 5.35 0.04 0.99 0.43 5.45 4.81 2.33 2.29 7.16 6.52 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-112 ? 1.5 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 2.90 0.05 1.28 0.50 2.95 2.63 2.44 2. 29 4.97 4.64 ns ?1 0.60 2.47 0.04 1.09 0.43 2.51 2.24 2.07 1.95 4.23 3.95 ns 4 ma std. 0.70 2.52 0.05 1.28 0.50 2.57 2.14 2.73 2.82 4.58 4.15 ns ?1 0.60 2.15 0.04 1.09 0.43 2.19 1.82 2.32 2.40 3.90 3.53 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-76 revision 13 1.2 v lvcmos (jesd8-12a) low-voltage cmos for 1.2 v complies with the lvcm os standard jesd8-12a for general purpose 1.2 v applications. it uses a 1.2 v input buffer and a push-pull output buffer. table 2-113 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 1.2 v lvcmos vil vih vol voh iol ioh iosh 1 iosl 1 iil 2 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma max. ma a a 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.26 0.25 * vcci 0.75 * vcci 2 2 tbd tbd 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-114 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 1.2 v lvcmos vil vih vol voh iol ioh iosh 1 iosl 1 iil 2 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma max. ma a a 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.26 0.25 * vcci 0.75 * vcci 2 2 tbd tbd 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-115 ? minimum and maximum dc input and output levels applicable to standard i/o banks 1.2 v lvcmos vil vih vol voh iol ioh iosh 1 iosl 1 iil 2 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma max. ma a a 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.26 0.25 * vcci 0.75 * vcci 2 2 tbd tbd 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray.
proasic3l low power flash fpgas revision 13 2-77 figure 2-11 ? ac loading table 2-116 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.20.65 note: *measuring point = vtrip. see table 2-27 on page 2-26 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
proasic3l dc and switching characteristics 2-78 revision 13 timing characteristics 1.2 v dc core voltage table 2-117 ? 1.2 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs unit s 2 ma std. 0.77 11.80 0.05 2.38 3.52 0.50 10.97 8.61 4.79 4.38 12.91 10.55 ns ?1 0.66 10.04 0.04 2.02 2.99 0.43 9. 33 7.32 4.08 3.72 10.98 8.97 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-118 ? 1.2 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to pro i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs unit s 2 ma std. 0.77 4.84 0.05 2.38 3.52 0.50 4.50 3.96 4.78 4.51 6.44 5.90 ns ?1 0.66 4.12 0.04 2.02 2.99 0.43 3.83 3.37 4.06 3.84 5.48 5.02 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-119 ? 1.2 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 8.77 0.05 1.82 0.50 6.17 5.45 2.80 2.77 8.11 7.39 ns ?1 0.60 7.46 0.04 1.55 0.43 5. 25 4.63 2.39 2.35 6.90 6.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-120 ? 1.2 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 3.73 0.05 1.82 0.50 2.48 2.06 2.80 2.89 4.42 4.00 ns ?1 0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-121 ? 1.2 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 9.67 0.05 1.83 0.50 6.78 5.99 4.08 4.57 8.72 7.93 ns ?1 0.60 8.23 0.04 1.56 0.43 5. 77 5.09 3.47 3.88 7.42 6.74 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-79 table 2-122 ? 1.2 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.70 4.17 0.05 1.83 0.50 2.79 2.48 4.23 4.55 4.73 4.42 ns ?1 0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-80 revision 13 1.2 v lvcmos wide range table 2-123 ? minimum and maximum dc input and output levels for lvcmos 1.2 v wide range applicable to pro i/o banks 1.2 v lvcmos wide range equivalent software default drive strength option 1 vil vih vol voh iol ioh iosh iosl iil iih drive strength min. v max. v min. v max. v max. v min. vaa max. ma 2 max. ma 2 a a 100 a 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 100 100 20 26 10 10 notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. currents are measured at 85c junction temperature. 3. all lvmcos 1.2 v software macros support lvcmos 3.3 v wide range as specified in the jdec8-12 specification 4. software default selection highlighted in gray. table 2-124 ? minimum and maximum dc input and output levels for lvcmos 1.2 wide range applicable to advanced i/o banks 1.2 v lvcmos wide range equivalent software default drive strength option 1 vil vih vol voh iol ioh iosh iosl iil iih drive strength min. v max. v min. v max. v max. v min. vaa max. ma 2 max. ma 2 a a 100 a 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 100 100 20 26 10 10 notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. currents are measured at 85c junction temperature. 3. all lvmcos 1.2 v software macros support lvcmos 3.3 v wide range as specified in the jdec8-12 specification 4. software default selection highlighted in gray. table 2-125 ? minimum and maximum dc input and output levels for lvcmos 1.2 v wide range applicable to standard plus i/o banks 1.2 v lvcmos wide range equivalent software default drive strength option 1 vil vih vol voh iol ioh iosh iosl iil iih drive strength min. v max. v min. v max. v max. v min. vaa max. ma 2 max. ma 2 a a 100 a 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.26 0.25 * vcci 0.75 * vcci 100 100 20 26 10 10 notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. currents are measured at 85c junction temperature. 3. all lvmcos 1.2 v software macros support lvcmos 3.3 v wide range as specified in the jdec8-12 specification 4. software default selection highlighted in gray.
proasic3l low power flash fpgas revision 13 2-81 3.3 v pci, 3.3 v pci-x peripheral component interface for 3.3 v standard specifies support for 33 mhz and 66 mhz pci bus applications. ac loadings are defined per the pci/pci-x specifications for the database; microsemi loadings for enable path characterization are described in figure 2-12 . ac loadings are defined per pci/pc i-x specifications for the datapath; microsemi loading for tristate is described in table 2-127 . timing characteristics 1.5 v dc core voltage table 2-126 ? minimum and maximum dc input and output levels 3.3 v pci/pci-x vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 per pci specification per pci curves 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-12 ? ac loading test point enable path r to vcci for t lz / t zl / t zls 10 pf for t zh / t zhs / t zl / t zls 10 pf for t hz / t lz r to gnd for t hz / t zh / t zhs r = 1 k test point datapath r = 25 r to vcci for t dp (f) r to gnd for t dp (r) table 2-127 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 3.3 0.285 * vcci for t dp(r) 0.615 * vcci for t dp(f) 10 note: *measuring point = vtrip. see table 2-27 on page 2-26 for a complete table of trip points. table 2-128 ? 3.3 v pci/pci-x ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to pro i/o banks speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 2.52 0.04 2.47 3.33 0.38 2.57 1.80 2.95 3.25 4.58 3.81 ns ?1 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-82 revision 13 1.2 v dc core voltage table 2-129 ? 3.3 v pci/pci-x ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/o banks speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.54 2.41 0.04 0.78 0.38 2.46 1.76 2.89 3.22 4.47 3.77 ns 0.54 ?1 0.46 2.05 0.03 0.66 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns 0.46 note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-130 ? 3.3 v pci/pci-x ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard plus i/o banks speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.54 2.08 0.04 0.77 0.38 2.12 1.53 2.51 2.90 4.13 3.55 ns 0.54 ?1 0.46 1.77 0.03 0.65 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns 0.46 note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-131 ? 3.3 v pci/pci-x ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to pro i/o banks speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 2.52 0.05 2.47 3.33 0.50 2.57 1.80 2.95 3.25 4.58 3.81 ns ?1 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-132 ? 3.3 v pci/pci-x ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to advanced i/o banks speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.70 2.41 0.05 0.78 0.50 2.46 1.76 2.89 3.22 4.47 3.77 0.73 ns ?1 0.60 2.05 0.04 0.66 0.43 2.09 1.49 2.46 2.74 3.80 3.21 0.62 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-133 ? 3.3 v pci/pci-x ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.70 2.08 0.05 0.77 0.50 2.12 1.53 2.51 2.90 4.13 3.55 0.73 ns ?1 0.60 1.77 0.04 0.65 0.43 1.80 1.31 2.14 2.47 3.51 3.02 0.62 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-83 voltage-referenced i/o characteristics 3.3 v gtl gunning transceiver logic is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an open-drain output buffer. the v cci pin should be connected to 3.3 v. table 2-134 ? minimum and maximum dc input and output levels 3.3 v gtl vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 20 ma 3 ?0.3 vref ? 0.05 vref + 0.05 3.6 0.4 ? 20 20 268 181 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. output drive strength is below jedec specification. figure 2-13 ? ac loading table 2-135 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.05 vref + 0.05 0.8 0.8 1.2 10 note: *measuring point = vtrip . see table 2-16 on page 2-12 for a complete tabl e of trip points. test point 10 pf 25 gtl v tt
proasic3l dc and switching characteristics 2-84 revision 13 timing characteristics table 2-136 ? 3.3 v gtl ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v vref = 0.8 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 1.87 0.04 2.12 0. 38 1.83 1.87 3.85 3.88 ns ?1 0.50 1.59 0.03 1.80 0. 33 1.56 1.59 3.27 3.30 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-137 ? 3.3 v gtl ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v vref = 0.8 v applicable to pro i/os speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 1.87 0.05 2.12 0. 50 1.83 1.87 3.85 3.88 ns ?1 0.66 1.59 0.04 1.80 0. 43 1.56 1.59 3.27 3.30 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-85 2.5 v gtl gunning transceiver logic is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an open-drain output buffer. the v cci pin should be connected to 2.5 v table 2-138 ? minimum and maximum dc input and output levels 2.5 gtl vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 20 ma 3 ?0.3 vref ? 0.05 vref + 0.05 2.7 0.4 ? 20 20 169 124 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. output drive strength is below jedec specification. figure 2-14 ? ac loading table 2-139 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.05 vref + 0.05 0.8 0.8 1.2 10 note: *measuring point = vtrip. see table 2-16 on page 2-12 for a complete table of trip points. test point 10 pf 25 gtl v tt
proasic3l dc and switching characteristics 2-86 revision 13 timing characteristics table 2-140 ? 2.5 v gtl ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v vref = 0.8 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 1.92 0.04 2.05 0. 38 1.95 1.92 3.96 3.93 ns ?1 0.50 1.63 0.03 1.75 0. 33 1.66 1.63 3.37 3.34 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-141 ? 2.5 v gtl ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v vref = 0.8 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 1.92 0.05 2.05 0. 50 1.95 1.92 3.96 3.93 ns ?1 0.66 1.63 0.04 1.75 0. 43 1.66 1.63 3.37 3.34 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-87 3.3 v gtl+ gunning transceiver logic plus is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an open-drain output buffer. the v cci pin should be connected to 3.3 v timing characteristics table 2-142 ? minimum and maximum dc input and output levels 3.3 v gtl+ vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 35 ma ?0.3 vref ? 0.1 vref + 0.1 3.6 0.6 ? 35 35 268 181 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-15 ? ac loading table 2-143 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.1 vref + 0.1 1.0 1.0 1.5 10 note: *measuring point = vtrip. see table 2-16 on page 2-12 for a complete table of trip points. test point 10 pf 25 gtl+ v tt table 2-144 ? 3.3 v gtl+ ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v vref = 1.0 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 1.85 0.04 2.12 0. 38 1.88 1.85 3.90 3.86 ns ?1 0.50 1.57 0.03 1.80 0. 33 1.60 1.57 3.31 3.29 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-145 ? 3.3 v gtl+ ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v vref = 1.0 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 1.85 0.05 2.12 0. 50 1.88 1.85 3.90 3.86 ns ?1 0.66 1.57 0.04 1.80 0. 43 1.60 1.57 3.31 3.29 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-88 revision 13 2.5 v gtl+ gunning transceiver logic plus is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an open-drain output buffer. the v cci pin should be connected to 2.5 v. table 2-146 ? minimum and maximum dc input and output levels 2.5 v gtl+ vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 33 ma ?0.3 vref ? 0.1 vref + 0.1 2.7 0.6 ? 33 33 169 124 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-16 ? ac loading table 2-147 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.1 vref + 0.1 1.0 1.0 1.5 10 note: *measuring point = vtrip. see table 2-16 on page 2-12 for a complete table of trip points. test point 10 pf 25 gtl+ v tt
proasic3l low power flash fpgas revision 13 2-89 timing characteristics table 2-148 ? 2.5 v gtl+ ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v vref = 1.0 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 1.99 0.04 2.05 0. 38 2.02 1.89 4.03 3.90 ns ?1 0.50 1.69 0.03 1.75 0. 33 1.72 1.61 3.43 3.32 ns note: for specific junction temperature an d voltage supply levels, refer to table 2-16 on page 2-12 for derating values. table 2-149 ? 2.5 v gtl+ ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v vref = 1.0 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 1.99 0.05 2.05 0. 50 2.02 1.89 4.03 3.90 ns ?1 0.66 1.69 0.04 1.75 0. 43 1.72 1.61 3.43 3.32 ns note: for specific junction temperature an d voltage supply levels, refer to table 2-16 on page 2-12 for derating values.
proasic3l dc and switching characteristics 2-90 revision 13 hstl class i high-speed transceiver logic is a general-purpo se high-speed 1.5 v bus standard (eia/jesd8-6). proasic3e devices support class i. this provides a differential amplifier input buffer and a push-pull output buffer. table 2-150 ? minimum and maximum dc input and output levels hstl class i vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 8 ma ?0.3 vref ? 0.1 vref + 0.1 1.575 0.4 vcci ? 0.4 8 8 32 39 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-17 ? ac loading table 2-151 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.1 vref + 0.1 0.75 0.75 0.75 20 note: *measuring point = vtrip . see table 2-16 on page 2-12 for a complete table of trip points. test point 20 pf 50 hstl class i v tt
proasic3l low power flash fpgas revision 13 2-91 timing characteristics table 2-152 ? hstl class i ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v vref = 0.75 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 2.86 0.04 2.50 0. 38 2.91 2.83 4.93 4.84 ns ?1 0.50 2.43 0.03 2.12 0. 33 2.48 2.41 4.19 4.12 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-153 ? hstl class i ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v vref = 0.75 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 2.86 0.05 2.50 0. 50 2.91 2.83 4.93 4.84 ns ?1 0.66 2.43 0.04 2.12 0. 43 2.48 2.41 4.19 4.12 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-92 revision 13 hstl class ii high-speed transceiver logic is a general-purpo se high-speed 1.5 v bus standard (eia/jesd8-6). proasic3e devices support class ii. this provides a differential amplifier input buffer and a push-pull output buffer. table 2-154 ? minimum and maximum dc input and output levels hstl class ii vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 15 ma 3 ?0.3 vref ? 0.1 vref + 0.1 1.575 0.4 vcci ? 0.4 15 15 66 55 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. output drive strength is below jedec specification. figure 2-18 ? ac loading table 2-155 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.1 vref + 0.1 0.75 0.75 0.75 20 note: *measuring point = vtrip. see table 2-16 on page 2-12 for a complete table of trip points. test point 20 pf 25 hstl class ii v tt
proasic3l low power flash fpgas revision 13 2-93 timing characteristics table 2-156 ? hstl class ii ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v vref = 0.75 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 2.72 0.04 2.50 0. 38 2.77 2.44 4.78 4.45 ns ?1 0.50 2.32 0.03 2.12 0. 33 2.36 2.08 4.07 3.79 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-157 ? hstl class ii ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v vref = 0.75 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 2.72 0.05 2.50 0. 50 2.77 2.44 4.78 4.45 ns ?1 0.66 2.32 0.04 2.12 0. 43 2.36 2.08 4.07 3.79 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-94 revision 13 sstl2 class i stub-speed terminated logic for 2.5 v memory bus standard (jesd8-9). proasic3e devices support class i. this provides a differential amplif ier input buffer and a push-pull output buffer. table 2-158 ? minimum and maximum dc input and output levels sstl2 class i vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 15 ma ?0.3 vref ? 0.2 vref + 0.2 2.7 0.54 vcci ? 0.62 15 15 83 87 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-19 ? ac loading table 2-159 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.2 vref + 0.2 1.25 1.25 1.25 30 note: *measuring point = vtrip. see table 2-16 on page 2-12 for a complete table of trip points. test point 30 pf 50 25 sstl2 class i v tt
proasic3l low power flash fpgas revision 13 2-95 timing characteristics table 2-160 ? sstl2 class i ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v vref = 1.25 v applicable to pro i/os speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 1.91 0.04 1.89 0. 38 1.95 1.66 1.95 1.66 ns ?1 0.50 1.63 0.03 1.61 0. 33 1.66 1.41 1.66 1.41 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-161 ? sstl2 class i ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v vref = 1.25 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 1.91 0.05 1.89 0. 50 1.95 1.66 1.95 1.66 ns ?1 0.66 1.63 0.04 1.61 0. 43 1.66 1.41 1.66 1.41 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-96 revision 13 sstl2 class ii stub-speed terminated logic for 2.5 v memory bus standard (jesd8-9). proasic3e devices support class ii. this provides a differential ampl ifier input buffer and a push-pull output buffer. timing characteristics table 2-162 ? minimum and maximum dc input and output levels sstl2 class ii vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 18 ma ?0.3 vref ? 0.2 vref + 0.2 2.7 0.35 vcci ? 0.43 18 18 169 124 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-20 ? ac loading table 2-163 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.2 vref + 0.2 1.25 1.25 1.25 30 note: *measuring point = vtrip. see table 2-16 on page 2-12 for a complete table of trip points. test point 30 pf 25 25 sstl2 class ii v tt table 2-164 ? sstl2 class ii ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v vref = 1.25 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 1.95 0.04 1.89 0. 38 1.99 1.59 1.99 1.59 ns ?1 0.50 1.66 0.03 1.61 0. 33 1.69 1.36 1.69 1.36 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-165 ? sstl2 class ii ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case v cci = 2.3 v vref = 1.25 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 1.95 0.05 1.89 0. 50 1.99 1.59 1.99 1.59 ns ?1 0.66 1.66 0.04 1.61 0. 43 1.69 1.36 1.69 1.36 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-97 sstl3 class i stub-speed terminated logic for 3.3 v memory bus standard (jesd8-8). proasic3e devices support class i. this provides a differential amplif ier input buffer and a push-pull output buffer. timing characteristics table 2-166 ? minimum and maximum dc input and output levels sstl3 class i vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 14 ma ?0.3 vref ? 0.2 vref + 0.2 3.6 0.7 vcci ? 1.1 14 14 51 54 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-21 ? ac loading table 2-167 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.2 vref + 0.2 1.5 1.5 1.485 30 note: *measuring point = vtrip. see table 2-16 on page 2-12 for a complete table of trip points. test point 30 pf 50 25 sstl3 class i v tt table 2-168 ? sstl3 class i ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v vref = 1.5 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 2.08 0.04 1.81 0. 38 2.11 1.65 2.11 1.65 ns ?1 0.50 1.77 0.03 1.54 0. 33 1.80 1.41 1.80 1.41 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-169 ? sstl3 class i ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v vref = 1.5 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 2.08 0.05 1.81 0. 50 2.11 1.65 2.11 1.65 ns ?1 0.66 1.77 0.04 1.54 0. 43 1.80 1.41 1.80 1.41 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-98 revision 13 sstl3 class ii stub-speed terminated logic for 3.3 v memory bus standard (jesd8-8). proasic3e devices support class ii. this provides a differential ampl ifier input buffer and a push-pull output buffer. timing characteristics table 2-170 ? minimum and maximum dc input and output levels sstl3 class ii vil vih vol voh iol ioh iosl iosh iil iih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 21 ma ?0.3 vref ? 0.2 vref + 0.2 3. 6 0.5 vcci ? 0.9 21 21 103 109 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-22 ? ac loading table 2-171 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.2 vref + 0.2 1.5 1.5 1.485 30 note: *measuring point = vtrip . see table 2-16 on page 2-12 for a complete tabl e of trip points. test point 30 pf 25 25 sstl3 class ii v tt table 2-172 ? sstl3 class ii ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v vref = 1.5 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.59 1.86 0.04 1.81 0. 38 1.89 1.50 1.89 1.50 ns ?1 0.50 1.58 0.03 1.54 0. 33 1.61 1.28 1.61 1.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-173 ? sstl3 class ii ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v vref = 1.5 v applicable to pro i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.77 1.86 0.05 1.81 0. 50 1.89 1.50 1.89 1.50 ns ?1 0.66 1.58 0.04 1.54 0. 43 1.61 1.28 1.61 1.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-99 differential i/o characteristics physical implementation configuration of the i/o modules as a differential pair is handled by designer software when the user instantiates a differential i/o macro in the design. differential i/os can also be used in conjuncti on with the embedded input r egister (inreg), output register (outreg), enable register (enreg), an d double data rate (ddr). however, there is no support for bidirectional i/os or tristates with the lvpecl standards. lvds low-voltage differential signaling (ansi/tia/eia-644 ) is a high-speed, differential i/o standard. it requires that one data bit be carried through two si gnal lines, so two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitte r and receiver is shown in an example in figure 2-23 . the building blocks of the lvds transmitter-receiver are one transmitte r macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvpecl implementation because the output standard specifications are different. along with lvds i/o, proasic3 also supports bu s lvds structure and multipoint lvds (m-lvds) configuration (up to 40 nodes). figure 2-23 ? lvds circuit diag ram and board-level implementation 140 ? 100 ? z 0 = 50 ? z 0 = 50 ? 165 ? 165 ? + ? p n p n inbuf_lvds outbuf_lvds fpga fpga bourns part number: cat16-lv4f12
proasic3l dc and switching characteristics 2-100 revision 13 table 2-174 ? minimum and maximum dc input and output levels dc parameter description min. typ. max. units vcci supply voltage 2.375 2.5 2.625 v vol output low voltage 0.9 1.075 1.25 v voh output high voltage 1.25 1.425 1.6 v iol 1 output lower current 0.65 0.91 1.16 ma ioh 1 output high current 0.65 0.91 1.16 ma v i input voltage 0 2.925 v iih 2 input high leakage current 10 a iil 2 input low leakage current 10 a vodiff differential output voltage 250 350 450 mv vocm output common mode voltage 1.125 1.25 1.375 v vicm input common mode voltage 0.05 1.25 2.35 v vidiff input differential voltage 100 350 mv notes: 1. currents are measured at 85c junction temperature. 2. iol/ioh is defined by vo diff/(resistor network). table 2-175 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.075 1.325 cross point note: *measuring point = v trip. see table 2-27 on page 2-26 for a complete table of trip points.
proasic3l low power flash fpgas revision 13 2-101 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-176 ? lvds ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to pro i/o banks speed grade t dout t dp t din t py units std. 0.59 1.65 0.04 2.18 ns ?1 0.50 1.40 0.03 1.85 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-177 ? lvds ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks speed grade t dout t dp t din t py units std. 0.54 1.65 0.04 1.44 ns ?1 0.46 1.40 0.03 1.23 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-178 ? lvds ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v applicable to pro i/o banks speed grade t dout t dp t din t py units std. 0.77 1.68 0.05 2.18 ns ?1 0.66 1.43 0.04 1.85 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-179 ? lvds ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v applicable to advanced i/o banks speed grade t dout t dp t din t py units std. 0.70 1.65 0.05 1.44 ns ?1 0.60 1.40 0.04 1.23 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-102 revision 13 b-lvds/m-lvds bus lvds (b-lvds) and multipoint lvds (m-lvds) s pecifications extend the existing lvds standard to high-performance multipoint bus applications. multid rop and multipoint bus configurations may contain any combination of drivers, receiv ers, and transceivers. microsemi lv ds drivers provide the higher drive current required by b-lvds and m-lvds to accomm odate the loading. the drivers require series terminations for better signal quality and to control voltage swing. termination is also required at both ends of the bus since the driver can be located anywhere on the bus. these configurations can be implemented using the tribuf_lvds and bibuf_lvds macros along with appr opriate terminations. multipoint designs using microsemi lvds macros can achieve up to 200 mhz with a maximum of 20 loads. a sample application is given in figure 2-24 . the input and output buffer delays are available in the lvds section in table 2-174 on page 2-100 . example: for a bus consisting of 20 equidistant lo ads, the following terminations provide the required differential voltage, in worst-case industrial operating conditions, at the farthest receiver: r s =60 ? and r t =70 ? , given z 0 =50 ? (2") and z stub =50 ? (~1.5"). figure 2-24 ? b-lvds/m-lvds multipoint application using lvds i/o buffers ... r t r t bibuf_lvds r + - t + - r + - t + - d + - en en en en en receiver transceiver receiver transceiver driver r s r s r s r s r s r s r s r s r s r s z stub z stub z stub z stub z stub z stub z stub z stub z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0
proasic3l low power flash fpgas revision 13 2-103 lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differ ential i/o standard. it requires that one data bit be carried through two signal lines . like lvds, two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitte r and receiver is shown in an example in figure 2-25 . the building blocks of the lvpecl transmitter-receiver are one transm itter macro, one rece iver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvds implementation beca use the output standard specifications are different. figure 2-25 ? lvpecl circuit diagram and board-level im plementation table 2-180 ? minimum and maximum dc input and output levels dc parameter description min. max. min. max. min. max. units vcci supply voltage 3.0 3.3 3.6 v vol output low voltage 0.96 1.27 1.06 1.43 1.30 1.57 v voh output high voltage 1.8 2.11 1.92 2.28 2.13 2.41 v vil, vih input low, input high voltages 0 3.6 0 3.6 0 3.6 v vodiff differential output voltage 0.625 0.97 0.625 0.97 0.625 0.97 v vocm output common-mode voltage 1.762 1.98 1.762 1.98 1.762 1.98 v vicm input common-mode voltage 1.01 2.57 1.01 2.57 1.01 2.57 v vidiff input differential voltage 300 300 300 mv table 2-181 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.64 1.94 cross point note: *measuring point = vtrip. see table 2-27 on page 2-26 for a complete table of trip points. 187 w 100 ? z 0 = 50 ? z 0 = 50 ? 100 ? 100 ? + ? p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga bourns part number: cat16-pc4f12
proasic3l dc and switching characteristics 2-104 revision 13 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-182 ? lvpecl ? applies to 1. 5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to pro i/o banks speed grade t dout t dp t din t py units std. 0.59 1.64 0.04 1.97 ns ?1 0.50 1.40 0.03 1.67 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-183 ? lvpecl ? applies to 1. 5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/o banks speed grade t dout t dp t din t py units std. 0.54 1.62 0.04 1.26 ns ?1 0.46 1.38 0.03 1.08 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-184 ? lvpecl ? applies to 1. 2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to pro i/o banks speed grade t dout t dp t din t py units std. 0.77 1.62 0.05 1.97 ns ?1 0.66 1.37 0.04 1.67 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-185 ? lvpecl ? applies to 1. 2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v applicable to advanced i/o banks speed grade t dout t dp t din t py units std. 0.70 1.62 0.05 1.26 ns ?1 0.60 1.38 0.04 1.08 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-105 i/o register specifications fully registered i/o buffers with synchronous enable and asynchronous preset figure 2-26 ? timing model of registered i/o buffers with synchronous enable and asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset positive-edge triggered data output register and enable output register with: active high enable active high preset postive-edge triggered pad out clk enable preset data_out data eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array
proasic3l dc and switching characteristics 2-106 revision 13 table 2-186 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of the output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the output enable register j, h t oesue enable setup time for the output enable register k, h t oehe enable hold time for the output enable register k, h t oepre2q asynchronous preset-to-q of the output enable register i, eout t oerempre asynchronous preset removal time for the output enable register i, h t oerecpre asynchronous preset recovery time for the output enable register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of th e input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a note: *see figure 2-26 on page 2-105 for more information.
proasic3l low power flash fpgas revision 13 2-107 fully registered i/o buffers with synchronous enable and asynchronous clear figure 2-27 ? timing model of the registered i/o buffers with synchronous enable and asynchronous clear enable clk pad out clk enable clr data_out data y aa eout dout core array dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_enable bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf data input i/o register with active high enable active high clear positive-edge triggered data output register and enable output register with active high enable active high clear positive-edge triggered
proasic3l dc and switching characteristics 2-108 revision 13 table 2-187 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time for the output data register ll, hh t orecclr asynchronous clear recovery time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the output enable register kk, hh t oehe enable hold time for the output enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enable register ii, hh t oerecclr asynchronous clear recovery time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear recovery time for the input data register dd, aa note: *see figure 2-27 on page 2-107 for more information.
proasic3l low power flash fpgas revision 13 2-109 input register figure 2-28 ? input register timing diagram 50% preset clear out_1 clk data enable t isue 50% 50% t isud t ihd 50% 50% t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
proasic3l dc and switching characteristics 2-110 revision 13 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-188 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t iclkq clock-to-q of the input data register 0.24 0.29 ns t isud data setup time for the i nput data register 0.27 0.31 ns t ihd data hold time for the input data register 0.00 0.00 ns t isue enable setup time for the input data register 0.38 0.45 ns t ihe enable hold time for the input data register 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.46 0.54 ns t ipre2q asynchronous preset-to-q of the input data register 0.46 0.54 ns t iremclr asynchronous clear removal time fo r the input data register 0.00 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.23 0.27 ns t irempre asynchronous preset removal time fo r the input data register 0.00 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.23 0.27 ns t iwclr asynchronous clear minimum pulse width for the input data register 0.19 0.22 ns t iwpre asynchronous preset minimum pulse widt h for the input data register 0.19 0.22 ns t ickmpwh clock minimum pulse width high for the input data register 0.31 0.36 ns t ickmpwl clock minimum pulse width low for the input data register 0.28 0.32 ns note: for specific junction te mperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-189 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t iclkq clock-to-q of the input data register 0.32 0.37 ns t isud data setup time for the i nput data register 0.35 0.41 ns t ihd data hold time for the input data register 0.00 0.00 ns t isue enable setup time for the input data register 0.50 0.58 ns t ihe enable hold time for the input data register 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.60 0.71 ns t ipre2q asynchronous preset-to-q of the input data register 0.60 0.71 ns t iremclr asynchronous clear removal time fo r the input data register 0.00 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.30 0.35 ns t irempre asynchronous preset removal time fo r the input data register 0.00 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.30 0.35 ns t iwclr asynchronous clear minimum pulse width for the input data register 0.19 0.22 ns t iwpre asynchronous preset minimum pulse widt h for the input data register 0.19 0.22 ns t ickmpwh clock minimum pulse width high for the input data register 0.31 0.36 ns t ickmpwl clock minimum pulse width low for the input data register 0.28 0.32 ns note: for specific junction te mperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-111 output register figure 2-29 ? output register timing diagram preset clear dout clk data_out enable t osue 50% 50% t osud t ohd 50% 50% t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
proasic3l dc and switching characteristics 2-112 revision 13 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-190 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t oclkq clock-to-q of the output data register 0.60 0.71 ns t osud data setup time for the output data register 0.32 0.37 ns t ohd data hold time for the output data register 0.00 0.00 ns t osue enable setup time for the outp ut data register 0.45 0.53 ns t ohe enable hold time for the output data register 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 0.82 0.96 ns t opre2q asynchronous preset-to-q of the output data register 0.82 0.96 ns t oremclr asynchronous clear removal time for the output data register 0.00 0.00 ns t orecclr asynchronous clear recovery time fo r the output data register 0.23 0.27 ns t orempre asynchronous preset removal time for the output data register 0.00 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.23 0.27 ns t owclr asynchronous clear minimum pulse width for the output data register 0.19 0.22 ns t owpre asynchronous preset minimum pulse width for the output data register 0.19 0.22 ns t ockmpwh clock minimum pulse width high for the output data register 0.31 0.36 ns t ockmpwl clock minimum pulse width low for the output data register 0.28 0.32 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-191 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t oclkq clock-to-q of the output data register 0.78 0.92 ns t osud data setup time for the output data register 0.42 0.49 ns t ohd data hold time for the output data register 0.00 0.00 ns t osue enable setup time for the outp ut data register 0.58 0.69 ns t ohe enable hold time for the output data register 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 1.07 1.26 ns t opre2q asynchronous preset-to-q of the output data register 1.07 1.26 ns t oremclr asynchronous clear removal time for the output data register 0.00 0.00 ns t orecclr asynchronous clear recovery time fo r the output data register 0.30 0.35 ns t orempre asynchronous preset removal time for the output data register 0.00 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.30 0.35 ns t owclr asynchronous clear minimum pulse width for the output data register 0.19 0.22 ns t owpre asynchronous preset minimum pulse width for the output data register 0.19 0.22 ns t ockmpwh clock minimum pulse width high for the output data register 0.31 0.36 ns t ockmpwl clock minimum pulse width low for the output data register 0.28 0.32 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-113 output enable register figure 2-30 ? output enable register timing diagram 50% preset clear eout clk d_enable enable t oesue 50% 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
proasic3l dc and switching characteristics 2-114 revision 13 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-192 ? output enable register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t oeclkq clock-to-q of the output enable register 0.45 0.53 ns t oesud data setup time for the output enable register 0.32 0.37 ns t oehd data hold time for the output enable register 0.00 0.00 ns t oesue enable setup time for the output enable register 0.44 0.52 ns t oehe enable hold time for the output enable register 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 0.68 0.80 ns t oepre2q asynchronous preset-to-q of the output enable register 0.68 0.80 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.23 0.27 ns t oerempre asynchronous preset removal time for the output enable register 0.00 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.23 0.27 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 0.22 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.19 0.22 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.31 0.36 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.28 0.32 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-193 ? output enable register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t oeclkq clock-to-q of the output enable register 0.59 0.70 ns t oesud data setup time for the output enable register 0.42 0.49 ns t oehd data hold time for the output enable register 0.00 0.00 ns t oesue enable setup time for the output enable register 0.58 0.68 ns t oehe enable hold time for the output enable register 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 0.89 1.04 ns t oepre2q asynchronous preset-to-q of the output enable register 0.89 1.04 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.30 0.35 ns t oerempre asynchronous preset removal time for the output enable register 0.00 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.30 0.35 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 0.22 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.19 0.22 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.31 0.36 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.28 0.32 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-115 ddr module specifications input ddr module figure 2-31 ? input ddr timing model table 2-194 ? parameter definitions parameter name parameter definition measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
proasic3l dc and switching characteristics 2-116 revision 13 timing characteristics 1.5 v dc core voltage figure 2-32 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 2-195 ? input ddr propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.28 0.33 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.40 0.47 ns t ddrisud1 data setup for input ddr (fall) 0.29 0.34 ns t ddrisud2 data setup for input ddr (rise) 0.25 0.29 ns t ddrihd1 data hold for input ddr (fall) 0.00 0.00 ns t ddrihd2 data hold for input ddr (rise) 0.00 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 0.47 0.55 ns t ddriclr2q2 asynchronous clear-to-out out_qf for input ddr 0.58 0.68 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.23 0.27 ns t ddriwclr asynchronous clear minimum puls e width for input ddr 0.18 0.22 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.31 0.36 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.28 0.32 ns f ddrimax maximum frequency for input ddr 250.00 250.00 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-117 1.2 v dc core voltage table 2-196 ? input ddr propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.43 0.37 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.61 0.52 ns t ddrisud1 data setup for input ddr (fall) 0.44 0.38 ns t ddrisud2 data setup for input ddr (rise) 0.39 0.33 ns t ddrihd1 data hold for input ddr (fall) 0.00 0.00 ns t ddrihd2 data hold for input ddr (rise) 0.00 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 0.73 0.62 ns t ddriclr2q2 asynchronous clear-to-out out_qf for input ddr 0.89 0.76 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.35 0.30 ns t ddriwclr asynchronous clear minimum puls e width for input ddr 0.22 0.19 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.36 0.31 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.32 0.28 ns f ddrimax maximum frequency for input ddr 160.00 160.00 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-118 revision 13 output ddr module figure 2-33 ? output ddr timing model table 2-197 ? parameter definitions parameter name parameter definition measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out output ddr ff1 0 1 x x x x x x x a b d e c c b outbuf data_r (from core)
proasic3l low power flash fpgas revision 13 2-119 timing characteristics 1.5 v dc core voltage figure 2-34 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddroremclr t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 2-198 ? output ddr propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t ddroclkq clock-to-out of ddr for output ddr 0.72 0.84 ns t ddrisud1 data_f data setup for output ddr 0.39 0.45 ns t ddrosud2 data_r data setup for output ddr 0.39 0.45 ns t ddrohd1 data_f data hold for output ddr 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 0.82 0.96 ns t ddroremclr asynchronous clear removal ti me for output ddr 0.00 0.00 ns t ddrorecclr asynchronous clear recovery ti me for output ddr 0.23 0.27 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.19 0.22 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.31 0.36 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.28 0.32 ns f ddomax maximum frequency for the output ddr 250.00 250.00 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-120 revision 13 1.2 v dc core voltage table 2-199 ? output ddr propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t ddroclkq clock-to-out of ddr for output ddr 1.10 0.94 ns t ddrisud1 data_f data setup for output ddr 0.59 0.50 ns t ddrosud2 data_r data setup for output ddr 0.59 0.50 ns t ddrohd1 data_f data hold for output ddr 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 1.26 1.07 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.35 0.30 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.22 0.19 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.36 0.31 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.32 0.28 ns f ddomax maximum frequency for the output ddr 160.00 160.00 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-121 versatile characteristics versatile specifications as a combinatorial module the proasic3 library offers all combinations of lut- 3 combinatorial functions. in this section, timing characteristics are presented for a sample of the library. for more details, refer to the igloo, ? fusion, and proasic3 macro library guide . figure 2-35 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
proasic3l dc and switching characteristics 2-122 revision 13 figure 2-36 ? timing model and waveforms t pd a b t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for the particular combinatorial cell y nand2 or any combinatorial logic t pd t pd 50% vcc vcc vcc 50% gnd a, b, c 50% 50% 50% (rr) (rf) gnd out out gnd 50% (ff) (fr) t pd t pd
proasic3l low power flash fpgas revision 13 2-123 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-200 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v combinatorial cell equation parameter ?1 std. units inv y =!a t pd 0.41 0.48 ns and2 y = a b t pd 0.48 0.57 ns nand2 y =!(a b) t pd 0.48 0.57 ns or2 y = a + b t pd 0.50 0.58 ns nor2 y =!(a + b) t pd 0.50 0.58 ns xor2 y = a ?? bt pd 0.75 0.88 ns maj3 y = maj(a, b, c) t pd 0.71 0.84 ns xor3 y = a ? b ?? ct pd 0.89 1.05 ns mux2 y = a !s + b s t pd 0.52 0.61 ns and3 y = a b c t pd 0.57 0.67 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-201 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v combinatorial cell equation parameter ?1 std. units inv y = !a t pd 0.54 0.63 ns and2 y = a b t pd 0.63 0.74 ns nand2 y = !(a b) t pd 0.63 0.74 ns or2 y = a + b t pd 0.65 0.76 ns nor2 y = !(a + b) t pd 0.65 0.76 ns xor2 y = a ?? bt pd 0.98 1.16 ns maj3 y = maj(a , b, c) t pd 0.93 1.09 ns xor3 y = a ? b ?? ct pd 1.17 1.37 ns mux2 y = a !s + b s t pd 0.68 0.79 ns and3 y = a b c t pd 0.75 0.88 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-124 revision 13 versatile specifications as a sequential module the proasic3 library offers a wide variety of sequentia l cells, including flip-flops and latches. each has a data input and optional enable, clear, or preset. in this section, timing characteristics are presented for a representative sample from the libra ry. for more details, refer to the igloo, fusion, and proasic3 macro library guide . figure 2-37 ? sample of sequential cells figure 2-38 ? timing model and waveforms dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
proasic3l low power flash fpgas revision 13 2-125 timing characteristics 1.5 v dc core voltage table 2-202 ? register delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t clkq clock-to-q of the core register 0.56 0.66 ns t sud data setup time for the core register 0.44 0.51 ns t hd data hold time for the core register 0.00 0.00 ns t sue enable setup time for the core register 0.46 0.55 ns t he enable hold time for the core register 0.00 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.41 0.48 ns t pre2q asynchronous preset-to-q of the core register 0.41 0.48 ns t remclr asynchronous clear removal time for the core register 0.00 0.00 ns t recclr asynchronous clear recovery time for the core register 0.23 0.27 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.23 0.27 ns t wclr asynchronous clear minimum pulse width for the core register 0.30 0.34 ns t wpre asynchronous preset minimum pulse width for the core register 0.30 0.34 ns t ckmpwh clock minimum pulse width high for the core register 0.56 0.64 ns t ckmpwl clock minimum pulse width low for the core register 0.56 0.64 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-126 revision 13 1.2 v dc core voltage table 2-203 ? register delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t clkq clock-to-q of the core register 0.73 0.86 ns t sud data setup time for the core register 0.57 0.67 ns t hd data hold time for the core register 0.00 0.00 ns t sue enable setup time for the core register 0.61 0.71 ns t he enable hold time for the core register 0.00 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.53 0.63 ns t pre2q asynchronous preset-to-q of the core register 0.53 0.63 ns t remclr asynchronous clear removal time for the core register 0.00 0.00 ns t recclr asynchronous clear recovery time for the core register 0.30 0.35 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.30 0.35 ns t wclr asynchronous clear minimum pulse width for the core register 0.30 0.34 ns t wpre asynchronous preset minimum pulse width for the core register 0.30 0.34 ns t ckmpwh clock minimum pulse width high for the core register 0.56 0.64 ns t ckmpwl clock minimum pulse width low for the core register 0.56 0.64 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-127 global resource characteristics a3p250l clock tree topology clock delays are device-specific. figure 2-39 is an example of a global tree used for clock routing. the global tree presented in figure 2-39 is driven by a ccc located on t he west side of the a3p250l device. it is used to drive all d- flip-flops in the device. figure 2-39 ? example of global tree use in an a3p250l device for clock routing central global rib versatile rows global spine ccc
proasic3l dc and switching characteristics 2-128 revision 13 global tree timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o standard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to the "clock conditioning circuits" section on page 2-132 . ta b l e 2 - 2 0 4 to table 2-210 on page 2-131 present minimum and maximum global clock delays within each device. minimum and maximum delays are measured with minimum and maximum loading. timing characteristics table 2-204 ? a3p250l global resource ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.82 1.06 0.96 1.25 ns t rckh input high delay for global clock 0.80 1.09 0.94 1.28 ns t rckmpwh minimum pulse width high for global clock 0.75 0.88 ns t rckmpwl minimum pulse width low for global clock 0.85 1.00 ns t rcksw maximum skew for global clock 0.29 0.34 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-205 ? a3p250l global resource ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.40 1.68 1.64 1.97 ns t rckh input high delay for global clock 1.38 1.71 1.62 2.01 ns t rckmpwh minimum pulse width high for global clock 1.05 1.24 ns t rckmpwl minimum pulse width low for global clock 1.23 1.44 ns t rcksw maximum skew for global clock 0.33 0.39 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-129 table 2-206 ? a3p600l global resource ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.90 1.14 1.06 1.34 ns t rckh input high delay for global clock 0.89 1.17 1.04 1.38 ns t rckmpwh minimum pulse width high for global clock 0.75 0.88 ns t rckmpwl minimum pulse width low for global clock 0.85 1.00 ns t rcksw maximum skew for global clock 0.28 0.33 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-207 ? a3p600l global resource ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.48 1.76 1.74 2.07 ns t rckh input high delay for global clock 1.47 1.80 1.72 2.11 ns t rckmpwh minimum pulse width high for global clock 1.05 1.24 ns t rckmpwl minimum pulse width low for global clock 1.23 1.44 ns t rcksw maximum skew for global clock 0.33 0.39 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-130 revision 13 table 2-208 ? a3p1000l global resource ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.02 1.26 1.20 1.48 ns t rckh input high delay for global clock 1.01 1.29 1.18 1.52 ns t rckmpwh minimum pulse width high for global clock 0.75 0.88 ns t rckmpwl minimum pulse width low for global clock 0.85 1.00 ns t rcksw maximum skew for global clock 0.28 0.33 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-209 ? a3p1000l global resource ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.61 1.89 1.89 2.22 ns t rckh input high delay for global clock 1.60 1.92 1.88 2.26 ns t rckmpwh minimum pulse width high for global clock 1.05 1.24 ns t rckmpwl minimum pulse width low for global clock 1.23 1.44 ns t rcksw maximum skew for global clock 0.33 0.39 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-131 table 2-210 ? a3pe3000l global resource ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.53 1.75 1.79 2.06 ns t rckh input high delay for global clock 1.51 1.77 1.78 2.08 ns t rckmpwh minimum pulse width high for global clock 0.75 0.88 ns t rckmpwl minimum pulse width low for global clock 0.85 1.00 ns t rcksw maximum skew for global clock 0.26 0.30 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-211 ? a3pe3000l global resource ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.52 1.94 1.78 2.28 ns t rckh input high delay for global clock 1.49 1.96 1.76 2.30 ns t rckmpwh minimum pulse width high for global clock 1.05 1.24 ns t rckmpwl minimum pulse width low for global clock 1.23 1.44 ns t rcksw maximum skew for global clock 0.47 0.55 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-132 revision 13 clock conditioning circuits ccc electrical specifications timing characteristics table 2-212 ? proasic3l ccc/pll specification ccc/pll operating at 1.2 v parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 250 mhz clock conditioning circuitry output frequency f out_ccc 0.75 250 mhz delay increments in programmable delay blocks 1, 2 270 3 ps number of programmable values in ea ch programmable delay block 32 serial clock (sclk) for dynamic pll 4 100 mhz input cycle-to-cycle jitter (peak magnitude) 1 ns ccc output peak-to-peak period jitter f ccc_out max peak-to-peak period jitter 1 global network used external fb used 3 global networks used 0.75 mhz to 24 mhz 0.50% 0.75% 0.70% 24 mhz to 100 mhz 1.00% 1.50% 1.20% 100 mhz to 250 mhz 2.50% 3.75% 2.75% acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 5 lockcontrol = 0 2 ns lockcontrol = 1 1 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 1.2 15.65 ns delay range in block: programmable delay 2 1, 2 0.025 15.65 ns delay range in block: fixed delay 1, 2 3.1 ns notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-7 for deratings. 2. t j = 25c, v cc = 1.2 v 3. when the ccc/pll core is generated by microsemi core generator software, not all delay values of the specified delay increments are available. refer to the libero soc online help for more information. 4. maximum value obtained for a ?1 speed grade device in worst-case commercial conditions. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. 5. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by the period jitter parameter.
proasic3l low power flash fpgas revision 13 2-133 table 2-213 ? proasic3l ccc/pll specification ccc/pll operating at 1.5 v parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 350 mhz clock conditioning circuitry output frequency f out_ccc 0.75 350 mhz delay increments in programmable delay blocks 1, 2 160 3 ps serial clock (sclk) for dynamic pll 4 110 number of programmable values in ea ch programmable delay block 32 input period jitter 1.5 ns ccc output peak-to-peak period jitter f ccc_out max peak-to-peak period jitter 1 global network used 3 global networks used 0.75 mhz to 24 mhz 0.50% 0.70% 24 mhz to 100 mhz 1.00% 1.20% 100 mhz to 250 mhz 1.75% 2.00 250 mhz to 350 mhz 2.50% 5.60% acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 5 lockcontrol = 0 1.6 ns lockcontrol = 1 0.8 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 0.6 5.56 ns delay range in block: programmable delay 2 1, 2 0.025 5.56 ns delay range in block: fixed delay 1, 2 2.2 ns notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-7 for deratings. 2. t j = 25c, vcc = 1.5 v 3. when the ccc/pll core is generated by microsemi core generator software, not all delay values of the specified delay increments are available. refer to the libero soc online help for more information. 4. maximum value obtained for a ?1 speed grade device in worst-case commercial conditions. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. 5. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by the period jitter parameter. note: peak-to-peak jitter meas urements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-40 ? peak-to-peak jitter definition t period_max t period_min output signal
proasic3l dc and switching characteristics 2-134 revision 13 embedded sram and fifo characteristics sram figure 2-41 ? ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
proasic3l low power flash fpgas revision 13 2-135 timing waveforms figure 2-42 ? ram read for pass-through output. applicable to both ram4k9 and ram512x18 . figure 2-43 ? ram read for pipelined output. appl icable to both ram4k9 and ram512x18. clk [r|w]add blk wen dout|rd a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk [r|w]add blk wen dout|rd a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
proasic3l dc and switching characteristics 2-136 revision 13 figure 2-44 ? ram write, output retained. applicable to both ram4k9 and ram512x18. figure 2-45 ? ram write, output as write data (wmode = 1). applicable to ram4k9 only. t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk wen [r|w]add din|wd d n dout|rd t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk wen addr din t bkh dout (pass-through) di 1 d n di 0 dout (pipelined) di 0 di 1 d n di 2
proasic3l low power flash fpgas revision 13 2-137 figure 2-46 ? ram reset. applicable to both ram4k9 and ram512x18. clk reset dout|rd d n t cyc t ckh t ckl t rstbq d m
proasic3l dc and switching characteristics 2-138 revision 13 timing characteristics table 2-214 ? ram4k9 ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t as address setup time 0.25 0.30 ns t ah address hold time 0.00 0.00 ns t ens ren, wen setup time 0.15 0.17 ns t enh ren, wen hold time 0.10 0.12 ns t bks blk setup time 0.24 0.28 ns t bkh blk hold time 0.02 0.02 ns t ds input data (din) setup time 0.19 0.22 ns t dh input data (din) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on dout (output retained, wmode = 0) 1.82 2.14 ns clock high to new data valid on dout (flow-through, wmode = 1) 2.40 2.83 ns t ckq2 clock high to new data valid on dout (pipelined) 0.91 1.07 ns t c2cwwl 1 address collision clk-to-clk delay for reliable write after write on same address ? applicable to closing edge 0.24 0.29 ns t c2crwh 1 address collision clk-to-clk delay for reliable read access after write on same address ? applicable to opening edge 0.20 0.24 ns t c2cwrh 1 address collision clk-to-clk delay for re liable write access after read on same address ? applicable to opening edge 0.25 0.30 ns t rstbq reset low to data out low on dout (flow-through) 0.94 1.11 ns reset low to data out low on dout (pipelined) 0.94 1.11 ns t remrstb reset removal 0.29 0.34 ns t recrstb reset recovery 1.53 1.80 ns t mpwrstb reset minimum pulse width 0.55 0.64 ns t cyc clock cycle time 5.10 5.87 ns f max maximum frequency 196 170 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-139 table 2-215 ? ram4k9 ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t as address setup time 0.33 0.39 ns t ah address hold time 0.00 0.00 ns t ens ren, wen setup time 0.19 0.22 ns t enh ren, wen hold time 0.13 0.15 ns t bks blk setup time 0.31 0.36 ns t bkh blk hold time 0.02 0.03 ns t ds input data (din) setup time 0.24 0.29 ns t dh input data (din) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on dout (output retained, wmode = 0) 2.38 2.80 ns clock high to new data valid on dout (flow-through, wmode = 1) 3.14 3.69 ns t ckq2 clock high to new data valid on dout (pipelined) 1.19 1.40 ns t c2cwwl 1 address collision clk-to-clk delay for reliable write after write on same address ? applicable to closing edge 0.25 0.30 ns t c2crwh 1 address collision clk-to-clk delay for reliable read access after write on same address ? applicable to opening edge 0.27 0.32 ns t c2cwrh 1 address collision clk-to-clk delay for re liable write access after read on same address ? applicable to opening edge 0.37 0.44 ns t rstbq reset low to data out low on dout (flow-through) 1.23 1.45 ns reset low to data out low on dout (pipeli ned) 1.23 1.45 ns t remrstb reset removal 0.38 0.45 ns t recrstb reset recovery 2.00 2.35 ns t mpwrstb reset minimum pulse width 0.63 0.72 ns t cyc clock cycle time 5.75 6.61 ns f max maximum frequency 174 151 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-140 revision 13 table 2-216 ? ram512x18 ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t as address setup time 0.25 0.30 ns t ah address hold time 0.00 0.00 ns t ens ren, wen setup time 0.09 0.11 ns t enh ren, wen hold time 0.06 0.07 ns t ds input data (wd) setup time 0.19 0.22 ns t dh input data (wd) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 2.20 2.59 ns t ckq2 clock high to new data valid on do (pipelined) 0.91 1.07 ns t c2crwh 1 address collision clk-to-clk delay for re liable read access after write on same address ? applicable to opening edge 0.18 0.21 ns t c2cwrh 1 address collision clk-to-clk delay for re liable write access after read on same address ? applicable to opening edge 0.21 0.25 ns t rstbq reset low to data out low on rd (flow through) 0.94 1.11 ns reset low to data out low on rd (pipelined) 0.94 1.11 ns t remrstb reset removal 0.29 0.34 ns t recrstb reset recovery 1.53 1.80 ns t mpwrstb reset minimum pulse width 0.55 0.64 ns t cyc clock cycle time 5.10 5.87 ns f max maximum frequency 196 170 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-141 table 2-217 ? ram512x18 ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t as address setup time 0.33 0.39 ns t ah address hold time 0.00 0.00 ns t ens ren, wen setup time 0.12 0.14 ns t enh ren, wen hold time 0.08 0.09 ns t ds input data (wd) setup time 0.24 0.29 ns t dh input data (wd) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on rd (output retained, wmode = 0) 2.88 3.39 ns t ckq2 clock high to new data valid on rd (pipelined) 1.19 1.40 ns t c2crwh 1 address collision clk-to-clk delay for re liable read access after write on same address ? applicable to opening edge 0.25 0.29 ns t c2cwrh 1 address collision clk-to-clk delay for re liable write access after read on same address ? applicable to opening edge 0.31 0.36 ns t rstbq reset low to data out low on rd (flow-through) 1.23 1.45 ns reset low to data out low on rd (pipelined) 1.23 1.45 ns t remrstb reset removal 0.38 0.45 ns t recrstb reset recovery 2.00 2.35 ns t mpwrstb reset minimum pulse width 0.63 0.72 ns t cyc clock cycle time 5.75 6.61 ns f max maximum frequency 174 151 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values
proasic3l dc and switching characteristics 2-142 revision 13 fifo figure 2-47 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
proasic3l low power flash fpgas revision 13 2-143 timing waveforms figure 2-48 ? fifo read figure 2-49 ? fifo write t ens t enh t ckq1 t ckq2 t cyc d 0 d 1 d n d n d 0 d 2 d 1 t bks t bkh rclk rblk ren rd (flow-through) rd (pipelined) wclk wen wd t ens t enh t ds t dh t cyc di 0 di 1 t bkh t bks wblk
proasic3l dc and switching characteristics 2-144 revision 13 figure 2-50 ? fifo reset figure 2-51 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter)
proasic3l low power flash fpgas revision 13 2-145 figure 2-52 ? fifo full flag and afull flag assertion figure 2-53 ? fifo empty flag and aempty flag deassertion figure 2-54 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull
proasic3l dc and switching characteristics 2-146 revision 13 timing characteristics table 2-218 ? fifo ? applies to 1.5 v dc core voltage worst commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?1 std. units t ens ren, wen setup time 1.40 1.65 ns t enh ren, wen hold time 0.02 0.02 ns t bks blk setup time 0.40 0.47 ns t bkh blk hold time 0.00 0.00 ns t ds input data (wd) setup time 0.19 0.22 ns t dh input data (wd) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on rd (flow-through) 2.40 2.83 ns t ckq2 clock high to new data valid on rd (pipelined) 0.91 1.07 ns t rckef rclk high to empty flag valid 1.75 2.06 ns t wckff wclk high to full flag valid 1.66 1.96 ns t ckaf clock high to almost empty/full flag valid 6.31 7.42 ns t rstfg reset low to empty/fu ll flag valid 1.73 2.03 ns t rstaf reset low to almost empty/ full flag valid 6.25 7.35 ns t rstbq reset low to data out low on rd (flow-through) 0.94 1.11 ns reset low to data out low on rd (pipelined) 0.94 1.11 ns t remrstb reset removal 0.29 0.34 ns t recrstb reset recovery 1.53 1.80 ns t mpwrstb reset minimum pulse width 0.55 0.64 ns t cyc clock cycle time 5.10 5.87 ns f max maximum frequency for fifo 196 170 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l low power flash fpgas revision 13 2-147 table 2-219 ? fifo ? applies to 1.2 v dc core voltage worst commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description ?1 std. units t ens ren, wen setup time 1.84 2.16 ns t enh ren, wen hold time 0.02 0.03 ns t bks blk setup time 0.40 0.47 ns t bkh blk hold time 0.00 0.00 ns t ds input data (wd) setup time 0.24 0.29 ns t dh input data (wd) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on rd (flow-through) 3.14 3.69 ns t ckq2 clock high to new data valid on rd (pipelined) 1.19 1.40 ns t rckef rclk high to empty flag valid 2.29 2.69 ns t wckff wclk high to full flag valid 2.18 2.56 ns t ckaf clock high to almost empty/full flag valid 8.25 9.70 ns t rstfg reset low to empty/fu ll flag valid 2.26 2.65 ns t rstaf reset low to almost empty/ full flag valid 8.17 9.60 ns t rstbq reset low to data out low on rd (flow-through) 1.23 1.45 ns reset low to data out low on rd (pipelined) 1.23 1.45 ns t remrstb reset removal 0.38 0.45 ns t recrstb reset recovery 2.00 2.35 ns t mpwrstb reset minimum pulse width 0.63 0.72 ns t cyc clock cycle time 5.75 6.61 ns f max maximum frequency for fifo 174 151 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.
proasic3l dc and switching characteristics 2-148 revision 13 embedded flashrom characteristics timing characteristics figure 2-55 ? timing diagram a 0 a 1 t su t hold t su t hold t su t hold t ckq2 t ckq2 t ckq2 clk a ddress data d 0 d 0 d 1 table 2-220 ? embedded flashrom access time ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t su address setup time 0.54 0.64 ns t hold address hold time 0.00 0.00 ns t ck2q clock to out 16.55 19.46 ns f max maximum clock frequency 15 15 mhz table 2-221 ? embedded flashrom access time? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t su address setup time 0.71 0.83 ns t hold address hold time 0.00 0.00 ns t ck2q clock to out 21.64 25.44 ns f max maximum clock frequency 15 15 mhz
proasic3l low power flash fpgas revision 13 2-149 jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtai n complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing characteristics in the "user i/o characteristics" section on page 2-18 for more details. timing characteristics table 2-222 ? jtag 1532 ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?1 std. units t disu test data input setup time 0.57 0.67 ns t dihd test data input hold time 1.13 1.33 ns t tmssu test mode select setup time 0.57 0.67 ns t tmdhd test mode select hold time 1.13 1.33 ns t tck2q clock to q (data out) 5.67 6.67 ns t rstb2q reset to q (data out) 22.67 26.67 ns f tckmax tck maximum frequency 24.00 21.00 mhz t trstrem resetb removal time 0.00 0.00 ns t trstrec resetb recovery time 0.23 0.27 ns t trstmpw resetb minimum pulse tbd tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values. table 2-223 ? jtag 1532 ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description ?1 std. units t disu test data input setup time 0.75 0.88 ns t dihd test data input hold time 1.50 1.76 ns t tmssu test mode select setup time 0.75 0.88 ns t tmdhd test mode select hold time 1.50 1.76 ns t tck2q clock to q (data out) 6.00 7.06 ns t rstb2q reset to q (data out) 25.00 29.41 ns f tckmax tck maximum frequency 20.00 17.00 mhz t trstrem resetb removal time 0.45 0.53 ns t trstrec resetb recovery time 0.00 0.00 ns t trstmpw resetb minimum pulse tbd tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-7 for derating values.

revision 13 3-1 3 ? pin descriptions and packaging supply pins gnd ground ground supply voltage to the core, i/o outputs, and i/o logic. gndq ground (quiet) quiet ground supply voltage to input buffers of i/o banks. within the package, the gndq plane is decoupled from the simultaneous switching noise orig inated from the output buffer ground domain. this minimizes the noise transfer within the package and im proves input signal integrity. gndq must always be connected to gnd on the board. vcc core supply voltage supply voltage to the fpga core, nominally 1.2 v or 1.5 v. vcc is required for powering the jtag state machine in addition to vjtag. even when a device is in bypass mode in a jtag chain of interconnected devices, both vcc and vjtag must remain powered to allow jtag signals to pass through the device. vcc can be switched dynamically from 1.2 v to 1.5 v or vice versa. this allo ws in-system programming (isp) when vcc is at 1.5 v and the benefit of low power operation when vcc is at 1.2 v. vccibx i/o supply voltage supply voltage to the bank's i/o output buffers and i/o logic. bx is the i/o bank number. there are up to eight i/o banks on proasic3l low power flash devices plus a dedicated vjtag bank. each bank can have a separate vcci connection. all i/os in a bank will run off the same vccibx supply. vcci can be 1.2 v, 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding vcci pins tied to gnd. vmvx i/o supply voltage (quiet) quiet supply voltage to the input buffers of each i/o bank. x is the bank number. within the package, the vmv plane biases the input stage of the i/os in the i/o banks. this minimizes the noise transfer within the package and improves input signal integrity. ea ch bank must have at least one vmv connection, and no vmv should be left unconnected. all i/os in a bank run off the same vmvx supply. vmv is used to provide a quiet supply voltage to the input buffers of each i/o bank. vmvx can be 1.2 v, 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding vmv pins tied to gnd. vmv and vcci should be at the same voltage within a given i/o bank. used vmv pins must be connected to the corresponding vcci pins of the same bank (i.e., vmv0 to vccib0, vmv1 to vccib1, etc.). vccpla/b/c/d/e/f pll supply voltage supply voltage to analog pll, nominally 1.5 v or 1.2 v for proasic3 devices when the plls are not used, the designer place-and -route tool automatically disables the unused plls to lower power consumption. the user should tie unused vccplx and vcomplx pins to ground. microsemi recommends tying vccplx to vcc and using proper filtering circuits to decouple vcc noise from the plls. refer to the pll power supply deco upling section of the "clock conditioning circuits in igloo and proasic3 devices" chapter of the proasic3l fpga fabric user?s guide for a complete board solution for the pll analog power supply and ground. there is one vccplf pin on proasic3l devices. vcompla/b/c/d/e/f pll ground ground to analog pll power supplies. when the plls are not used, the designer place-and-route tool automatically disables the unused plls to lower power consumption. the user should tie unused vccplx and vcomplx pins to ground. there is one vcomplf pin on proasic3l devices.
pin descriptions and packaging 3-2 revision 13 vjtag jtag supply voltage proasic3l devices have a separate bank for the dedi cated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). isolating t he jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned for use, the vjtag pin t ogether with the trst pin c ould be tied to gnd. it should be noted that vcc is required to be powered fo r jtag operation; vjtag alone is insufficient. if a device is in a jtag chain of interconnected boar ds, the board containing the device can be powered down, provided both vjtag and vcc to the part rema in powered; otherwise, jtag signals will not be able to transition the device, even in bypass mode. microsemi recommends that vpump and vjtag pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. vpump programming supply voltage proasic3ldevices support single-voltage isp of the configuration flash and flashrom. for programming, vpump should be 3.3 v nominal. duri ng normal device operation, vpump can be left floating or can be tied (pulled up) to any voltage between 0 v and the vpump maximum. programming power supply voltage (vpump) range is listed in the datasheet. when the vpump pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. for proper programming, 0.01 f and 0.33 f capacitors (both rated at 16 v) are to be connected in parallel across vpump and gnd, and positioned as close to the fpga pins as possible. microsemi recommends that vpump and vjtag pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. user pins i/o user input/output the i/o pin functions as an input, output, tristate, or bi directional buffer. input and output signal levels are compatible with the i/o standard selected. during programming, i/os become tristated and weakly pulled up to vcci. with vcci, vmv, and vcc supplies continuously powered up, when the device tr ansitions from programming to operating mode, the i/os are instantly configured to the desired user configuration. unused i/os are configured as follows: ? output buffer is disabled (with tristate value of high impedance) ? input buffer is disabled (with tristate value of high impedance) ? weak pull-up is programmed gl globals gl i/os have access to certain clock conditioning circuitry (and the pll) and/or have direct access to the global network (spines). additionally, the global i/os can be used as regular i/os, since they have identical capabilities. unused gl pins are configured as inputs with pull-up resistors. see more detailed descriptions of global i/o connecti vity in the "clock conditioning circuits in igloo and proasic3 devices" chapter of the proasic3l fpga fabric user?s guide . all inputs labeled gc/gf are direct inputs into the quadrant clocks. for exampl e, if gaa0 is used for an input, gaa1 and gaa2 are no longer available for input to the quadrant global s. all inputs labeled gc/gf are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. the inputs to the global network are multiplexed, and only one input can be used as a global input. refer to the "i/o structur es in igloo and proasic3 devices" chapter of the proasic3l fpga fabric user?s guide for an explanation of the naming of global pins. ff flash*freeze mode activation pin flash*freeze mode is available on proasic3l devices. the ff pin is a dedicated input pin used to enter and exit flash*freeze mode. the ff pin is active low, has the same characteristics as a single-ended i/o, and must meet the maximum rise and fall times. when flash*freeze mode is not used in the design, the ff pin is available as a regular i/o.
proasic3l low power flash fpgas revision 13 3-3 when flash*freeze mode is used, the ff pin must not be left floating, to avoid accidentally entering flash*freeze mode. while in flash*freeze mode, the flash*freeze pin should be constantly asserted. the flash*freeze pin can be used with any single- ended i/o standard supported by the i/o bank in which the pin is located, and input signal levels compatible with the i/o standard selected. the ff pin should be treated as a sensitive asynchronous signa l. when defining pin placement and board layout, simultaneously switching outputs (ssos) and their effects on sensitive asynchronous pins must be considered. unused ff or i/o pins are tristated with weak pul l-up. this default config uration applies to both flash*freeze mode and normal operation mo de. no user intervention is required. table 3-1 shows the flash*freeze pin location on the available packages proasic3l devices. the flash*freeze pin location is independent of device (except for the pq208 package), allowing migration to larger or smaller devices while maintaining the same pin location on the board. refer to the "flash*freeze technology and low power modes" chapter of the proasic3l fpga fabric user?s guide for more information on i/o states during flash*freeze mode. table 3-1 ? flash*freeze pin location proasic3l package flash*freeze pin vq100 27 fg144 l3 fg256 t3 FG324 r5 fg484 w6 fg896 ah4 pq208 pq208-a3p250 pq208-a3p600l pq208-a3p1000l pq208-a3p3000l 56 55 55 58
pin descriptions and packaging 3-4 revision 13 jtag pins proasic3l devices have a separate bank for the dedi cated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). vcc must also be powered for the jtag state machine to operate, even if the device is in bypass mode; vjtag alone is insufficient. both vjtag and vcc to the part must be supplied to allow jtag signals to transition the device. isolating the jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned for use, the vjtag pin together with the trst pin could be tied to gnd. tck test clock test clock input for jtag boundary scan, isp, and ujtag. the tck pin does not have an internal pull-up/-down resistor. if jtag is not used, microsemi recommends tying off tck to gnd through a resistor placed close to the fpga pin. this prevent s jtag operation in case tms enters an undesired state. note that to operate at all vjtag voltages, 500 ? to 1 k ? will satisfy the requirements. refer to table 3-2 for more in formation. tdi test data input serial input for jtag boundary scan, isp, and ujtag us age. there is an internal weak pull-up resistor on the tdi pin. tdo test data output serial output for jtag boundary scan, isp, and ujtag usage. tms test mode select the tms pin controls the use of the ieee 1532 boundar y scan pins (tck, tdi, tdo, trst). there is an internal weak pull-up resistor on the tms pin. trst boundary scan reset pin the trst pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the trst pin. if jtag is not used, an external pull- down resistor could be included to ensure the test access port (tap) is held in reset mode. the resistor values must be chosen from ta b l e 3 - 2 and must satisfy the parallel re sistance value requirement. the values in ta b l e 3 - 2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a jtag chain. in critical applications, an upset in the jtag circui t could allow entrance to an undesired jtag state. in such cases, microsemi recommends tying off trst to gnd through a resistor placed close to the fpga pin. note that to operate at all vjtag voltages, 500 ? to 1 k ? will satisfy the requirements. table 3-2 ? recommended tie-off values for the tck and trst pins vjtag tie-off resistance vjtag at 3.3 v 200 ? to 1 k ? vjtag at 2.5 v 200 ? to 1 k ? vjtag at 1.8 v 500 ? to 1 k ? vjtag at 1.5 v 500 ? to 1 k ? notes: 1. equivalent parallel resistance if more than one device is on the jtag chain 2. the tck pin can be pulled up/down. 3. the trst pin is pulled down.
proasic3l low power flash fpgas revision 13 3-5 special function pins nc no connect this pin is not connected to circuitry within the devic e. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. dc do not connect this pin should not be connected to any signals on the pcb. these pins should be left unconnected. packaging semiconductor technology is constantly shrinking in size while growing in capability and functional integration. to enable next-generation silicon tech nologies, semiconductor packages have also evolved to provide improved performance and flexibility. microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability an d performance. microsemi ic packaging technology efficiently supports high-density fpgas with large-pin- count ball grid arrays (bga s), but is also flexible enough to accommodate stringent form factor requi rements for chip scale packaging (csp). in addition, microsemi offers a variety of packages designed to meet your most dema nding application and economic requirements for today's embedded and mobile systems. related documents user?s guides proasicl fpga fabric user?s guide http://www.microsemi.com/s oc/documents/pa3l_ug.pdf packaging the following documents provide packaging information and device selection for low power flash devices. product catalog http://www.microsemi.com/soc /documents/prodcat_pib.pdf lists devices currently recommended for new designs and the packages available for each member of the family. use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. package mechanical drawings http://www.microsemi.com/soc /documents/pckgmechdrwngs.pdf this document contains the package mechanical dr awings for all packages currently or previously supplied by microsemi. use the bookmarks to na vigate to the package mechanical drawings. additional packaging materials: http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx .

revision 13 4-1 4 ? package pin assignments vq100 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com./soc/pr oducts/solutions/package/docs.aspx . note: this is the top view of the package. 1 100
package pin assignments 4-2 revision 13 vq100 pin number a3p250l function 1gnd 2 gaa2/io118udb3 3 io118vdb3 4 gab2/io117udb3 5 io117vdb3 6 gac2/io116udb3 7 io116vdb3 8 io112psb3 9gnd 10 gfb1/io109pdb3 11 gfb0/io109ndb3 12 vcomplf 13 gfa0/io108npb3 14 vccplf 15 gfa1/io108ppb3 16 gfa2/io107psb3 17 vcc 18 vccib3 19 gfc2/io105psb3 20 gec1/io100pdb3 21 gec0/io100ndb3 22 gea1/io98pdb3 23 gea0/io98ndb3 24 vmv3 25 gndq 26 gea2/io97rsb2 27 ff/geb2/io96rsb2 28 gec2/io95rsb2 29 io93rsb2 30 io92rsb2 31 io91rsb2 32 io90rsb2 33 io88rsb2 34 io86rsb2 35 io85rsb2 36 io84rsb2 37 vcc 38 gnd 39 vccib2 40 io77rsb2 41 io74rsb2 42 io71rsb2 43 gdc2/io63rsb2 44 gdb2/io62rsb2 45 gda2/io61rsb2 46 gndq 47 tck 48 tdi 49 tms 50 vmv2 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io60usb1 58 gdc0/io58vdb1 59 gdc1/io58udb1 60 io52ndb1 61 gcb2/io52pdb1 62 gca1/io50pdb1 63 gca0/io50ndb1 64 gcc0/io48ndb1 65 gcc1/io48pdb1 66 vccib1 67 gnd 68 vcc 69 io43ndb1 70 gbc2/io43pdb1 71 gbb2/io42psb1 72 io41ndb1 vq100 pin number a3p250l function 73 gba2/io41pdb1 74 vmv1 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io29rsb0 83 io27rsb0 84 io25rsb0 85 io23rsb0 86 io21rsb0 87 vccib0 88 gnd 89 vcc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 gac1/io05rsb0 94 gac0/io04rsb0 95 gab1/io03rsb0 96 gab0/io02rsb0 97 gaa1/io01rsb0 98 gaa0/io00rsb0 99 gndq 100 vmv0 vq100 pin number a3p250l function
proasic3l low power flash fpgas revision 13 4-3 pq208 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the top view of the package. 208-pin pqfp 1 208
package pin assignments 4-4 revision 13 pq208 pin number a3pl250 function 1gnd 2 gaa2/io118udb3 3 io118vdb3 4 gab2/io117udb3 5 io117vdb3 6 gac2/io116udb3 7 io116vdb3 8 io115udb3 9 io115vdb3 10 io114udb3 11 io114vdb3 12 io113pdb3 13 io113ndb3 14 io112pdb3 15 io112ndb3 16 vcc 17 gnd 18 vccib3 19 io111pdb3 20 io111ndb3 21 gfc1/io110pdb3 22 gfc0/io110ndb3 23 gfb1/io109pdb3 24 gfb0/io109ndb3 25 vcomplf 26 gfa0/io108npb3 27 vccplf 28 gfa1/io108ppb3 29 gnd 30 gfa2/io107pdb3 31 io107ndb3 32 gfb2/io106pdb3 33 io106ndb3 34 gfc2/io105pdb3 35 io105ndb3 36 nc 37 io104pdb3 38 io104ndb3 39 io103psb3 40 vccib3 41 gnd 42 io101pdb3 43 io101ndb3 44 gec1/io100pdb3 45 gec0/io100ndb3 46 geb1/io99pdb3 47 geb0/io99ndb3 48 gea1/io98pdb3 49 gea0/io98ndb3 50 vmv3 51 gndq 52 gnd 53 nc 54 nc 55 gea2/io97rsb2 56 ff/geb2/io96rsb2 57 gec2/io95rsb2 58 io94rsb2 59 io93rsb2 60 io92rsb2 61 io91rsb2 62 vccib2 63 io90rsb2 64 io89rsb2 65 gnd 66 io88rsb2 67 io87rsb2 68 io86rsb2 69 io85rsb2 70 io84rsb2 71 vcc 72 vccib2 pq208 pin number a3pl250 function 73 io83rsb2 74 io82rsb2 75 io81rsb2 76 io80rsb2 77 io79rsb2 78 io78rsb2 79 io77rsb2 80 io76rsb2 81 gnd 82 io75rsb2 83 io74rsb2 84 io73rsb2 85 io72rsb2 86 io71rsb2 87 io70rsb2 88 vcc 89 vccib2 90 io69rsb2 91 io68rsb2 92 io67rsb2 93 io66rsb2 94 io65rsb2 95 io64rsb2 96 gdc2/io63rsb2 97 gnd 98 gdb2/io62rsb2 99 gda2/io61rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 vpump 107 nc 108 tdo pq208 pin number a3pl250 function
proasic3l low power flash fpgas revision 13 4-5 109 trst 110 vjtag 111 gda0/io60vdb1 112 gda1/io60udb1 113 gdb0/io59vdb1 114 gdb1/io59udb1 115 gdc0/io58vdb1 116 gdc1/io58udb1 117 io57vdb1 118 io57udb1 119 io56ndb1 120 io56pdb1 121 io55rsb1 122 gnd 123 vccib1 124 nc 125 nc 126 vcc 127 io53ndb1 128 gcc2/io53pdb1 129 gcb2/io52psb1 130 gnd 131 gca2/io51psb1 132 gca1/io50pdb1 133 gca0/io50ndb1 134 gcb0/io49ndb1 135 gcb1/io49pdb1 136 gcc0/io48ndb1 137 gcc1/io48pdb1 138 io47ndb1 139 io47pdb1 140 vccib1 141 gnd 142 vcc 143 io46rsb1 144 io45ndb1 pq208 pin number a3pl250 function 145 io45pdb1 146 io44ndb1 147 io44pdb1 148 io43ndb1 149 gbc2/io43pdb1 150 io42ndb1 151 gbb2/io42pdb1 152 io41ndb1 153 gba2/io41pdb1 154 vmv1 155 gndq 156 gnd 157 nc 158 gba1/io40rsb0 159 gba0/io39rsb0 160 gbb1/io38rsb0 161 gbb0/io37rsb0 162 gnd 163 gbc1/io36rsb0 164 gbc0/io35rsb0 165 io34rsb0 166 io33rsb0 167 io32rsb0 168 io31rsb0 169 io30rsb0 170 vccib0 171 vcc 172 io29rsb0 173 io28rsb0 174 io27rsb0 175 io26rsb0 176 io25rsb0 177 io24rsb0 178 gnd 179 io23rsb0 180 io22rsb0 pq208 pin number a3pl250 function 181 io21rsb0 182 io20rsb0 183 io19rsb0 184 io18rsb0 185 io17rsb0 186 vccib0 187 vcc 188 io16rsb0 189 io15rsb0 190 io14rsb0 191 io13rsb0 192 io12rsb0 193 io11rsb0 194 io10rsb0 195 gnd 196 io09rsb0 197 io08rsb0 198 io07rsb0 199 io06rsb0 200 vccib0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 pq208 pin number a3pl250 function
package pin assignments 4-6 revision 13 pq208 pin number a3pl600 function 1gnd 2 gaa2/io174pdb3 3 io174ndb3 4 gab2/io173pdb3 5 io173ndb3 6 gac2/io172pdb3 7 io172ndb3 8 io171pdb3 9 io171ndb3 10 io170pdb3 11 io170ndb3 12 io169pdb3 13 io169ndb3 14 io168pdb3 15 io168ndb3 16 vcc 17 gnd 18 vccib3 19 io166pdb3 20 io166ndb3 21 gfc1/io164pdb3 22 gfc0/io164ndb3 23 gfb1/io163pdb3 24 gfb0/io163ndb3 25 vcomplf 26 gfa0/io162npb3 27 vccplf 28 gfa1/io162ppb3 29 gnd 30 gfa2/io161pdb3 31 io161ndb3 32 gfb2/io160pdb3 33 io160ndb3 34 gfc2/io159pdb3 35 io159ndb3 36 vcc 37 io152pdb3 38 io152ndb3 39 io150psb3 40 vccib3 41 gnd 42 io147pdb3 43 io147ndb3 44 gec1/io146pdb3 45 gec0/io146ndb3 46 geb1/io145pdb3 47 geb0/io145ndb3 48 gea1/io144pdb3 49 gea0/io144ndb3 50 vmv3 51 gndq 52 gnd 53 vmv2 54 gea2/io143rsb2 55 ff/geb2/io142rsb2 56 gec2/io141rsb2 57 io140rsb2 58 io139rsb2 59 io138rsb2 60 io137rsb2 61 io136rsb2 62 vccib2 63 io135rsb2 64 io133rsb2 65 gnd 66 io131rsb2 67 io129rsb2 68 io127rsb2 69 io125rsb2 70 io123rsb2 71 vcc 72 vccib2 pq208 pin number a3pl600 function 73 io120rsb2 74 io119rsb2 75 io118rsb2 76 io117rsb2 77 io116rsb2 78 io115rsb2 79 io114rsb2 80 io112rsb2 81 gnd 82 io111rsb2 83 io110rsb2 84 io109rsb2 85 io108rsb2 86 io107rsb2 87 io106rsb2 88 vcc 89 vccib2 90 io104rsb2 91 io102rsb2 92 io100rsb2 93 io98rsb2 94 io96rsb2 95 io92rsb2 96 gdc2/io91rsb2 97 gnd 98 gdb2/io90rsb2 99 gda2/io89rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 vpump 107 gndq 108 tdo pq208 pin number a3pl600 function
proasic3l low power flash fpgas revision 13 4-7 109 trst 110 vjtag 111 gda0/io88ndb1 112 gda1/io88pdb1 113 gdb0/io87ndb1 114 gdb1/io87pdb1 115 gdc0/io86ndb1 116 gdc1/io86pdb1 117 io84ndb1 118 io84pdb1 119 io82ndb1 120 io82pdb1 121 io81psb1 122 gnd 123 vccib1 124 io77ndb1 125 io77pdb1 126 nc 127 io74ndb1 128 gcc2/io74pdb1 129 gcb2/io73psb1 130 gnd 131 gca2/io72psb1 132 gca1/io71pdb1 133 gca0/io71ndb1 134 gcb0/io70ndb1 135 gcb1/io70pdb1 136 gcc0/io69ndb1 137 gcc1/io69pdb1 138 io67ndb1 139 io67pdb1 140 vccib1 141 gnd 142 vcc 143 io65psb1 144 io64ndb1 pq208 pin number a3pl600 function 145 io64pdb1 146 io63ndb1 147 io63pdb1 148 io62ndb1 149 gbc2/io62pdb1 150 io61ndb1 151 gbb2/io61pdb1 152 io60ndb1 153 gba2/io60pdb1 154 vmv1 155 gndq 156 gnd 157 vmv0 158 gba1/io59rsb0 159 gba0/io58rsb0 160 gbb1/io57rsb0 161 gbb0/io56rsb0 162 gnd 163 gbc1/io55rsb0 164 gbc0/io54rsb0 165 io52rsb0 166 io50rsb0 167 io48rsb0 168 io46rsb0 169 io44rsb0 170 vccib0 171 vcc 172 io36rsb0 173 io35rsb0 174 io34rsb0 175 io33rsb0 176 io32rsb0 177 io31rsb0 178 gnd 179 io29rsb0 180 io28rsb0 pq208 pin number a3pl600 function 181 io27rsb0 182 io26rsb0 183 io25rsb0 184 io24rsb0 185 io23rsb0 186 vccib0 187 vcc 188 io20rsb0 189 io19rsb0 190 io18rsb0 191 io17rsb0 192 io16rsb0 193 io14rsb0 194 io12rsb0 195 gnd 196 io10rsb0 197 io09rsb0 198 io08rsb0 199 io07rsb0 200 vccib0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 pq208 pin number a3pl600 function
package pin assignments 4-8 revision 13 pq208 pin number apl1000 function 1gnd 2 gaa2/io225pdb3 3 io225ndb3 4 gab2/io224pdb3 5 io224ndb3 6 gac2/io223pdb3 7 io223ndb3 8 io222pdb3 9 io222ndb3 10 io220pdb3 11 io220ndb3 12 io218pdb3 13 io218ndb3 14 io216pdb3 15 io216ndb3 16 vcc 17 gnd 18 vccib3 19 io212pdb3 20 io212ndb3 21 gfc1/io209pdb3 22 gfc0/io209ndb3 23 gfb1/io208pdb3 24 gfb0/io208ndb3 25 vcomplf 26 gfa0/io207npb3 27 vccplf 28 gfa1/io207ppb3 29 gnd 30 gfa2/io206pdb3 31 io206ndb3 32 gfb2/io205pdb3 33 io205ndb3 34 gfc2/io204pdb3 35 io204ndb3 36 vcc 37 io199pdb3 38 io199ndb3 39 io197psb3 40 vccib3 41 gnd 42 io191pdb3 43 io191ndb3 44 gec1/io190pdb3 45 gec0/io190ndb3 46 geb1/io189pdb3 47 geb0/io189ndb3 48 gea1/io188pdb3 49 gea0/io188ndb3 50 vmv3 51 gndq 52 gnd 53 vmv2 54 gea2/io187rsb2 55 ff/geb2/io186rsb2 56 gec2/io185rsb2 57 io184rsb2 58 io183rsb2 59 io182rsb2 60 io181rsb2 61 io180rsb2 62 vccib2 63 io178rsb2 64 io176rsb2 65 gnd 66 io174rsb2 67 io172rsb2 68 io170rsb2 69 io168rsb2 70 io166rsb2 71 vcc 72 vccib2 pq208 pin number apl1000 function 73 io162rsb2 74 io160rsb2 75 io158rsb2 76 io156rsb2 77 io154rsb2 78 io152rsb2 79 io150rsb2 80 io148rsb2 81 gnd 82 io143rsb2 83 io141rsb2 84 io139rsb2 85 io137rsb2 86 io135rsb2 87 io133rsb2 88 vcc 89 vccib2 90 io128rsb2 91 io126rsb2 92 io124rsb2 93 io122rsb2 94 io120rsb2 95 io118rsb2 96 gdc2/io116rsb2 97 gnd 98 gdb2/io115rsb2 99 gda2/io114rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 vpump 107 gndq 108 tdo pq208 pin number apl1000 function
proasic3l low power flash fpgas revision 13 4-9 109 trst 110 vjtag 111 gda0/io113ndb1 112 gda1/io113pdb1 113 gdb0/io112ndb1 114 gdb1/io112pdb1 115 gdc0/io111ndb1 116 gdc1/io111pdb1 117 io109ndb1 118 io109pdb1 119 io106ndb1 120 io106pdb1 121 io104psb1 122 gnd 123 vccib1 124 io99ndb1 125 io99pdb1 126 nc 127 io96ndb1 128 gcc2/io96pdb1 129 gcb2/io95psb1 130 gnd 131 gca2/io94psb1 132 gca1/io93pdb1 133 gca0/io93ndb1 134 gcb0/io92ndb1 135 gcb1/io92pdb1 136 gcc0/io91ndb1 137 gcc1/io91pdb1 138 io88ndb1 139 io88pdb1 140 vccib1 141 gnd 142 vcc 143 io86psb1 144 io84ndb1 pq208 pin number apl1000 function 145 io84pdb1 146 io82ndb1 147 io82pdb1 148 io80ndb1 149 gbc2/io80pdb1 150 io79ndb1 151 gbb2/io79pdb1 152 io78ndb1 153 gba2/io78pdb1 154 vmv1 155 gndq 156 gnd 157 vmv0 158 gba1/io77rsb0 159 gba0/io76rsb0 160 gbb1/io75rsb0 161 gbb0/io74rsb0 162 gnd 163 gbc1/io73rsb0 164 gbc0/io72rsb0 165 io70rsb0 166 io67rsb0 167 io63rsb0 168 io60rsb0 169 io57rsb0 170 vccib0 171 vcc 172 io54rsb0 173 io51rsb0 174 io48rsb0 175 io45rsb0 176 io42rsb0 177 io40rsb0 178 gnd 179 io38rsb0 180 io35rsb0 pq208 pin number apl1000 function 181 io33rsb0 182 io31rsb0 183 io29rsb0 184 io27rsb0 185 io25rsb0 186 vccib0 187 vcc 188 io22rsb0 189 io20rsb0 190 io18rsb0 191 io16rsb0 192 io15rsb0 193 io14rsb0 194 io13rsb0 195 gnd 196 io12rsb0 197 io11rsb0 198 io10rsb0 199 io09rsb0 200 vccib0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 pq208 pin number apl1000 function
package pin assignments 4-10 revision 13 pq208 pin number a3pe3000l function 1gnd 2 gndq 3vmv7 4 gab2/io308psb7v4 5 gaa2/io309pdb7v4 6 io309ndb7v4 7 gac2/io307pdb7v4 8 io307ndb7v4 9 io303pdb7v3 10 io303ndb7v3 11 io299pdb7v3 12 io299ndb7v3 13 io295pdb7v2 14 io295ndb7v2 15 io291psb7v2 16 vcc 17 gnd 18 vccib7 19 io285pdb7v1 20 io285ndb7v1 21 io279psb7v0 22 gfc1/io275psb7v0 23 gfb1/io274pdb7v0 24 gfb0/io274ndb7v0 25 vcomplf 26 gfa0/io273npb6v4 27 vccplf 28 gfa1/io273ppb6v4 29 gnd 30 gfa2/io272pdb6v4 31 io272ndb6v4 32 gfb2/io271ppb6v4 33 gfc2/io270ppb6v4 34 io271npb6v4 35 io270npb6v4 36 vcc 36 vcc 37 io252pdb6v2 38 io252ndb6v2 39 io248psb6v1 40 vccib6 41 gnd 42 io244pdb6v1 43 io244ndb6v1 44 gec1/io236pdb6v0 45 gec0/io236ndb6v0 46 geb1/io235ppb6v0 47 gea1/io234ppb6v0 48 geb0/io235npb6v0 49 gea0/io234npb6v0 50 vmv6 51 gndq 52 gnd 53 vmv5 54 gndq 55 io233ndb5v4 56 gea2/io233pdb5v4 57 io232ndb5v4 58 ff/geb2/io232pdb5v4 59 io231ndb5v4 60 gec2/io231pdb5v4 61 io230psb5v4 62 vccib5 62 vccib5 63 io218ndb5v3 64 io218pdb5v3 65 gnd 66 io214psb5v2 67 io212ndb5v2 68 io212pdb5v2 69 io208ndb5v1 70 io208pdb5v1 pq208 pin number a3pe3000l function 71 vcc 72 vccib5 73 io202ndb5v1 74 io202pdb5v1 75 io198ndb5v0 76 io198pdb5v0 77 io197ndb5v0 78 io197pdb5v0 79 io194ndb5v0 80 io194pdb5v0 81 gnd 82 io184ndb4v3 83 io184pdb4v3 84 io180ndb4v3 85 io180pdb4v3 86 io176ndb4v2 87 io176pdb4v2 88 vcc 89 vccib4 90 io170ndb4v2 91 io170pdb4v2 92 io166ndb4v1 93 io166pdb4v1 94 io156ndb4v0 95 gdc2/io156pdb4v0 96 io154npb4v0 97 gnd 98 gdb2/io155psb4v0 99 gda2/io154ppb4v0 100 gndq 101 tck 102 tdi 103 tms 104 vmv4 105 gnd 106 vpump pq208 pin number a3pe3000l function
proasic3l low power flash fpgas revision 13 4-11 107 gndq 108 tdo 109 trst 110 vjtag 111 vmv3 112 gda0/io153npb3v4 113 gdb0/io152npb3v4 114 gda1/io153ppb3v4 115 gdb1/io152ppb3v4 116 gdc0/io151ndb3v4 117 gdc1/io151pdb3v4 118 io134ndb3v2 119 io134pdb3v2 120 io132ndb3v2 121 io132pdb3v2 122 gnd 123 vccib3 124 gcc2/io117psb3v0 125 gcb2/io116psb3v0 126 nc 127 io115ndb3v0 128 gca2/io115pdb3v0 129 gca1/io114ppb3v0 130 gnd 131 vccplc 132 gca0/io114npb3v0 133 vcomplc 134 gcb0/io113ndb2v3 135 gcb1/io113pdb2v3 136 gcc1/io112psb2v3 137 io110ndb2v3 138 io110pdb2v3 139 io106psb2v3 140 vccib2 141 gnd 142 vcc pq208 pin number a3pe3000l function 143 io99ndb2v2 144 io99pdb2v2 145 io96ndb2v1 146 io96pdb2v1 147 io91ndb2v1 148 io91pdb2v1 149 io88ndb2v0 150 io88pdb2v0 151 gbc2/io84psb2v0 152 gba2/io82psb2v0 153 gbb2/io83psb2v0 154 vmv2 155 gndq 156 gnd 157 vmv1 158 gndq 159 gba1/io81pdb1v4 160 gba0/io81ndb1v4 161 gbb1/io80pdb1v4 162 gnd 163 gbb0/io80ndb1v4 164 gbc1/io79pdb1v4 165 gbc0/io79ndb1v4 166 io74pdb1v4 167 io74ndb1v4 168 io70pdb1v3 169 io70ndb1v3 170 vccib1 171 vcc 171 vcc 172 io56psb1v1 173 io55pdb1v1 174 io55ndb1v1 175 io54pdb1v1 176 io54ndb1v1 177 io40pdb0v4 pq208 pin number a3pe3000l function 178 gnd 179 io40ndb0v4 180 io37pdb0v4 181 io37ndb0v4 182 io35pdb0v4 183 io35ndb0v4 184 io32pdb0v3 185 io32ndb0v3 186 vccib0 187 vcc 188 io28pdb0v3 189 io28ndb0v3 190 io24pdb0v2 191 io24ndb0v2 192 io21psb0v2 193 io16pdb0v1 194 io16ndb0v1 195 gnd 196 io11pdb0v1 197 io11ndb0v1 198 io08pdb0v0 199 io08ndb0v0 200 vccib0 201 gac1/io02pdb0v0 202 gac0/io02ndb0v0 203 gab1/io01pdb0v0 204 gab0/io01ndb0v0 205 gaa1/io00pdb0v0 206 gaa0/io00ndb0v0 207 gndq 208 vmv0 pq208 pin number a3pe3000l function
package pin assignments 4-12 revision 13 fg144 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the bottom view of the package. 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m a1 ball pad corner
proasic3l low power flash fpgas revision 13 4-13 fg144 pin number a3p250l function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io16rsb0 a6 gnd a7 io29rsb0 a8 vcc a9 io33rsb0 a10 gba0/io39rsb0 a11 gba1/io40rsb0 a12 gndq b1 gab2/io117udb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io14rsb0 b6 io19rsb0 b7 io22rsb0 b8 io30rsb0 b9 gbb0/io37rsb0 b10 gbb1/io38rsb0 b11 gnd b12 vmv1 c1 io117vdb3 c2 gfa2/io107ppb3 c3 gac2/io116udb3 c4 vcc c5 io12rsb0 c6 io17rsb0 c7 io24rsb0 c8 io31rsb0 c9 io34rsb0 c10 gba2/io41pdb1 c11 io41ndb1 c12 gbc2/io43ppb1 d1 io112ndb3 d2 io112pdb3 d3 io116vdb3 d4 gaa2/io118upb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io35rsb0 d8 gbc1/io36rsb0 d9 gbb2/io42pdb1 d10 io42ndb1 d11 io43npb1 d12 gcb1/io49ppb1 e1 vcc e2 gfc0/io110ndb3 e3 gfc1/io110pdb3 e4 vccib3 e5 io118vpb3 e6 vccib0 e7 vccib0 e8 gcc1/io48pdb1 e9 vccib1 e10 vcc e11 gca0/io50ndb1 e12 io51ndb1 f1 gfb0/io109npb3 f2 vcomplf f3 gfb1/io109ppb3 f4 io107npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io48ndb1 f9 gcb0/io49npb1 f10 gnd f11 gca1/io50pdb1 f12 gca2/io51pdb1 fg144 pin number a3p250l function g1 gfa1/io108ppb3 g2 gnd g3 vccplf g4 gfa0/io108npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io58upb1 g9 io53ndb1 g10 gcc2/io53pdb1 g11 io52ndb1 g12 gcb2/io52pdb1 h1 vcc h2 gfb2/io106pdb3 h3 gfc2/io105psb3 h4 gec1/io100pdb3 h5 vcc h6 io79rsb2 h7 io65rsb2 h8 gdb2/io62rsb2 h9 gdc0/io58vpb1 h10 vccib1 h11 io54psb1 h12 vcc j1 geb1/io99pdb3 j2 io106ndb3 j3 vccib3 j4 gec0/io100ndb3 j5 io88rsb2 j6 io81rsb2 j7 vcc j8 tck j9 gda2/io61rsb2 j10 tdo j11 gda1/io60udb1 j12 gdb1/io59udb1 fg144 pin number a3p250l function
package pin assignments 4-14 revision 13 k1 geb0/io99ndb3 k2 gea1/io98pdb3 k3 gea0/io98ndb3 k4 gea2/io97rsb2 k5 io90rsb2 k6 io84rsb2 k7 gnd k8 io66rsb2 k9 gdc2/io63rsb2 k10 gnd k11 gda0/io60vdb1 k12 gdb0/io59vdb1 l1 gnd l2 vmv3 l3 ff/geb2/io96rsb2 l4 io91rsb2 l5 vccib2 l6 io82rsb2 l7 io80rsb2 l8 io72rsb2 l9 tms l10 vjtag l11 vmv2 l12 trst m1 gndq m2 gec2/io95rsb2 m3 io92rsb2 m4 io89rsb2 m5 io87rsb2 m6 io85rsb2 m7 io78rsb2 m8 io76rsb2 m9 tdi m10 vccib2 m11 vpump m12 gndq fg144 pin number a3p250l function
proasic3l low power flash fpgas revision 13 4-15 fg144 pin number a3p600l function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io10rsb0 a6 gnd a7 io34rsb0 a8 vcc a9 io50rsb0 a10 gba0/io58rsb0 a11 gba1/io59rsb0 a12 gndq b1 gab2/io173pdb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io13rsb0 b6 io19rsb0 b7 io31rsb0 b8 io39rsb0 b9 gbb0/io56rsb0 b10 gbb1/io57rsb0 b11 gnd b12 vmv1 c1 io173ndb3 c2 gfa2/io161ppb3 c3 gac2/io172pdb3 c4 vcc c5 io16rsb0 c6 io25rsb0 c7 io28rsb0 c8 io42rsb0 c9 io45rsb0 c10 gba2/io60pdb1 c11 io60ndb1 c12 gbc2/io62ppb1 d1 io169pdb3 d2 io169ndb3 d3 io172ndb3 d4 gaa2/io174ppb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io54rsb0 d8 gbc1/io55rsb0 d9 gbb2/io61pdb1 d10 io61ndb1 d11 io62npb1 d12 gcb1/io70ppb1 e1 vcc e2 gfc0/io164ndb3 e3 gfc1/io164pdb3 e4 vccib3 e5 io174npb3 e6 vccib0 e7 vccib0 e8 gcc1/io69pdb1 e9 vccib1 e10 vcc e11 gca0/io71ndb1 e12 io72ndb1 f1 gfb0/io163npb3 f2 vcomplf f3 gfb1/io163ppb3 f4 io161npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io69ndb1 f9 gcb0/io70npb1 f10 gnd f11 gca1/io71pdb1 f12 gca2/io72pdb1 fg144 pin number a3p600l function g1 gfa1/io162ppb3 g2 gnd g3 vccplf g4 gfa0/io162npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io86ppb1 g9 io74ndb1 g10 gcc2/io74pdb1 g11 io73ndb1 g12 gcb2/io73pdb1 h1 vcc h2 gfb2/io160pdb3 h3 gfc2/io159psb3 h4 gec1/io146pdb3 h5 vcc h6 io80pdb1 h7 io80ndb1 h8 gdb2/io90rsb2 h9 gdc0/io86npb1 h10 vccib1 h11 io84psb1 h12 vcc j1 geb1/io145pdb3 j2 io160ndb3 j3 vccib3 j4 gec0/io146ndb3 j5 io129rsb2 j6 io131rsb2 j7 vcc j8 tck j9 gda2/io89rsb2 j10 tdo j11 gda1/io88pdb1 j12 gdb1/io87pdb1 fg144 pin number a3p600l function
package pin assignments 4-16 revision 13 k1 geb0/io145ndb3 k2 gea1/io144pdb3 k3 gea0/io144ndb3 k4 gea2/io143rsb2 k5 io119rsb2 k6 io111rsb2 k7 gnd k8 io94rsb2 k9 gdc2/io91rsb2 k10 gnd k11 gda0/io88ndb1 k12 gdb0/io87ndb1 l1 gnd l2 vmv3 l3 ff/geb2/io142rsb2 l4 io136rsb2 l5 vccib2 l6 io115rsb2 l7 io103rsb2 l8 io97rsb2 l9 tms l10 vjtag l11 vmv2 l12 trst m1 gndq m2 gec2/io141rsb2 m3 io138rsb2 m4 io123rsb2 m5 io126rsb2 m6 io134rsb2 m7 io108rsb2 m8 io99rsb2 m9 tdi m10 vccib2 m11 vpump m12 gndq fg144 pin number a3p600l function
proasic3l low power flash fpgas revision 13 4-17 fg144 pin number a3p1000l function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io10rsb0 a6 gnd a7 io44rsb0 a8 vcc a9 io69rsb0 a10 gba0/io76rsb0 a11 gba1/io77rsb0 a12 gndq b1 gab2/io224pdb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io13rsb0 b6 io26rsb0 b7 io35rsb0 b8 io60rsb0 b9 gbb0/io74rsb0 b10 gbb1/io75rsb0 b11 gnd b12 vmv1 c1 io224ndb3 c2 gfa2/io206ppb3 c3 gac2/io223pdb3 c4 vcc c5 io16rsb0 c6 io29rsb0 c7 io32rsb0 c8 io63rsb0 c9 io66rsb0 c10 gba2/io78pdb1 c11 io78ndb1 c12 gbc2/io80ppb1 d1 io213pdb3 d2 io213ndb3 d3 io223ndb3 d4 gaa2/io225ppb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io72rsb0 d8 gbc1/io73rsb0 d9 gbb2/io79pdb1 d10 io79ndb1 d11 io80npb1 d12 gcb1/io92ppb1 e1 vcc e2 gfc0/io209ndb3 e3 gfc1/io209pdb3 e4 vccib3 e5 io225npb3 e6 vccib0 e7 vccib0 e8 gcc1/io91pdb1 e9 vccib1 e10 vcc e11 gca0/io93ndb1 e12 io94ndb1 f1 gfb0/io208npb3 f2 vcomplf f3 gfb1/io208ppb3 f4 io206npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io91ndb1 f9 gcb0/io92npb1 f10 gnd f11 gca1/io93pdb1 f12 gca2/io94pdb1 fg144 pin number a3p1000l function g1 gfa1/io207ppb3 g2 gnd g3 vccplf g4 gfa0/io207npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io111ppb1 g9 io96ndb1 g10 gcc2/io96pdb1 g11 io95ndb1 g12 gcb2/io95pdb1 h1 vcc h2 gfb2/io205pdb3 h3 gfc2/io204psb3 h4 gec1/io190pdb3 h5 vcc h6 io105pdb1 h7 io105ndb1 h8 gdb2/io115rsb2 h9 gdc0/io111npb1 h10 vccib1 h11 io101psb1 h12 vcc j1 geb1/io189pdb3 j2 io205ndb3 j3 vccib3 j4 gec0/io190ndb3 j5 io160rsb2 j6 io157rsb2 j7 vcc j8 tck j9 gda2/io114rsb2 j10 tdo j11 gda1/io113pdb1 j12 gdb1/io112pdb1 fg144 pin number a3p1000l function
package pin assignments 4-18 revision 13 k1 geb0/io189ndb3 k2 gea1/io188pdb3 k3 gea0/io188ndb3 k4 gea2/io187rsb2 k5 io169rsb2 k6 io152rsb2 k7 gnd k8 io117rsb2 k9 gdc2/io116rsb2 k10 gnd k11 gda0/io113ndb1 k12 gdb0/io112ndb1 l1 gnd l2 vmv3 l3 ff/geb2/io186rsb2 l4 io172rsb2 l5 vccib2 l6 io153rsb2 l7 io144rsb2 l8 io140rsb2 l9 tms l10 vjtag l11 vmv2 l12 trst m1 gndq m2 gec2/io185rsb2 m3 io173rsb2 m4 io168rsb2 m5 io161rsb2 m6 io156rsb2 m7 io145rsb2 m8 io141rsb2 m9 tdi m10 vccib2 m11 vpump m12 gndq fg144 pin number a3p1000l function
proasic3l low power flash fpgas revision 13 4-19 fg256 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the bottom view of the package. 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a a1 ball pad corner
package pin assignments 4-20 revision 13 fg256 pin number a3p250l function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io07rsb0 a6 io10rsb0 a7 io11rsb0 a8 io15rsb0 a9 io20rsb0 a10 io25rsb0 a11 io29rsb0 a12 io33rsb0 a13 gbb1/io38rsb0 a14 gba0/io39rsb0 a15 gba1/io40rsb0 a16 gnd b1 gab2/io117udb3 b2 gaa2/io118udb3 b3 nc b4 gab1/io03rsb0 b5 io06rsb0 b6 io09rsb0 b7 io12rsb0 b8 io16rsb0 b9 io21rsb0 b10 io26rsb0 b11 io30rsb0 b12 gbc1/io36rsb0 b13 gbb0/io37rsb0 b14 nc b15 gba2/io41pdb1 b16 io41ndb1 c1 io117vdb3 c2 io118vdb3 c3 nc c4 nc c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io13rsb0 c8 io17rsb0 c9 io22rsb0 c10 io27rsb0 c11 io31rsb0 c12 gbc0/io35rsb0 c13 io34rsb0 c14 nc c15 io42npb1 c16 io44pdb1 d1 io114vdb3 d2 io114udb3 d3 gac2/io116udb3 d4 nc d5 gndq d6 io08rsb0 d7 io14rsb0 d8 io18rsb0 d9 io23rsb0 d10 io28rsb0 d11 io32rsb0 d12 gndq d13 nc d14 gbb2/io42ppb1 d15 nc d16 io44ndb1 e1 io113pdb3 e2 nc e3 io116vdb3 e4 io115udb3 e5 vmv0 e6 vccib0 e7 vccib0 e8 io19rsb0 fg256 pin number a3p250l function e9 io24rsb0 e10 vccib0 e11 vccib0 e12 vmv1 e13 gbc2/io43pdb1 e14 io46rsb1 e15 nc e16 io45pdb1 f1 io113ndb3 f2 io112ppb3 f3 nc f4 io115vdb3 f5 vccib3 f6 gnd f7 vcc f8 vcc f9 vcc f10 vcc f11 gnd f12 vccib1 f13 io43ndb1 f14 nc f15 io47ppb1 f16 io45ndb1 g1 io111ndb3 g2 io111pdb3 g3 io112npb3 g4 gfc1/io110ppb3 g5 vccib3 g6 vcc g7 gnd g8 gnd g9 gnd g10 gnd g11 vcc g12 vccib1 fg256 pin number a3p250l function
proasic3l low power flash fpgas revision 13 4-21 g13 gcc1/io48ppb1 g14 io47npb1 g15 io54pdb1 g16 io54ndb1 h1 gfb0/io109npb3 h2 gfa0/io108ndb3 h3 gfb1/io109ppb3 h4 vcomplf h5 gfc0/io110npb3 h6 vcc h7 gnd h8 gnd h9 gnd h10 gnd h11 vcc h12 gcc0/io48npb1 h13 gcb1/io49ppb1 h14 gca0/io50npb1 h15 nc h16 gcb0/io49npb1 j1 gfa2/io107ppb3 j2 gfa1/io108pdb3 j3 vccplf j4 io106ndb3 j5 gfb2/io106pdb3 j6 vcc j7 gnd j8 gnd j9 gnd j10 gnd j11 vcc j12 gcb2/io52ppb1 j13 gca1/io50ppb1 j14 gcc2/io53ppb1 j15 nc j16 gca2/io51pdb1 fg256 pin number a3p250l function k1 gfc2/io105pdb3 k2 io107npb3 k3 io104ppb3 k4 nc k5 vccib3 k6 vcc k7 gnd k8 gnd k9 gnd k10 gnd k11 vcc k12 vccib1 k13 io52npb1 k14 io55rsb1 k15 io53npb1 k16 io51ndb1 l1 io105ndb3 l2 io104npb3 l3 nc l4 io102rsb3 l5 vccib3 l6 gnd l7 vcc l8 vcc l9 vcc l10 vcc l11 gnd l12 vccib1 l13 gdb0/io59vpb1 l14 io57vdb1 l15 io57udb1 l16 io56pdb1 m1 io103pdb3 m2 nc m3 io101npb3 m4 gec0/io100npb3 fg256 pin number a3p250l function m5 vmv3 m6 vccib2 m7 vccib2 m8 nc m9 io74rsb2 m10 vccib2 m11 vccib2 m12 vmv2 m13 nc m14 gdb1/io59upb1 m15 gdc1/io58udb1 m16 io56ndb1 n1 io103ndb3 n2 io101ppb3 n3 gec1/io100ppb3 n4 nc n5 gndq n6 gea2/io97rsb2 n7 io86rsb2 n8 io82rsb2 n9 io75rsb2 n10 io69rsb2 n11 io64rsb2 n12 gndq n13 nc n14 vjtag n15 gdc0/io58vdb1 n16 gda1/io60udb1 p1 geb1/io99pdb3 p2 geb0/io99ndb3 p3 nc p4 nc p5 io92rsb2 p6 io89rsb2 p7 io85rsb2 p8 io81rsb2 fg256 pin number a3p250l function
package pin assignments 4-22 revision 13 p9 io76rsb2 p10 io71rsb2 p11 io66rsb2 p12 nc p13 tck p14 vpump p15 trst p16 gda0/io60vdb1 r1 gea1/io98pdb3 r2 gea0/io98ndb3 r3 nc r4 gec2/io95rsb2 r5 io91rsb2 r6 io88rsb2 r7 io84rsb2 r8 io80rsb2 r9 io77rsb2 r10 io72rsb2 r11 io68rsb2 r12 io65rsb2 r13 gdb2/io62rsb2 r14 tdi r15 nc r16 tdo t1 gnd t2 io94rsb2 t3 ff/geb2/io96rsb2 t4 io93rsb2 t5 io90rsb2 t6 io87rsb2 t7 io83rsb2 t8 io79rsb2 t9 io78rsb2 t10 io73rsb2 t11 io70rsb2 t12 gdc2/io63rsb2 fg256 pin number a3p250l function t13 io67rsb2 t14 gda2/io61rsb2 t15 tms t16 gnd fg256 pin number a3p250l function
proasic3l low power flash fpgas revision 13 4-23 fg256 pin number a3p600l function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io11rsb0 a6 io16rsb0 a7 io18rsb0 a8 io28rsb0 a9 io34rsb0 a10 io37rsb0 a11 io41rsb0 a12 io43rsb0 a13 gbb1/io57rsb0 a14 gba0/io58rsb0 a15 gba1/io59rsb0 a16 gnd b1 gab2/io173pdb3 b2 gaa2/io174pdb3 b3 gndq b4 gab1/io03rsb0 b5 io13rsb0 b6 io14rsb0 b7 io21rsb0 b8 io27rsb0 b9 io32rsb0 b10 io38rsb0 b11 io42rsb0 b12 gbc1/io55rsb0 b13 gbb0/io56rsb0 b14 io52rsb0 b15 gba2/io60pdb1 b16 io60ndb1 c1 io173ndb3 c2 io174ndb3 c3 vmv3 c4 io07rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io20rsb0 c8 io24rsb0 c9 io33rsb0 c10 io39rsb0 c11 io44rsb0 c12 gbc0/io54rsb0 c13 io51rsb0 c14 vmv0 c15 io61npb1 c16 io63pdb1 d1 io171ndb3 d2 io171pdb3 d3 gac2/io172pdb3 d4 io06rsb0 d5 gndq d6 io10rsb0 d7 io19rsb0 d8 io26rsb0 d9 io30rsb0 d10 io40rsb0 d11 io45rsb0 d12 gndq d13 io50rsb0 d14 gbb2/io61ppb1 d15 io53rsb0 d16 io63ndb1 e1 io166pdb3 e2 io167npb3 e3 io172ndb3 e4 io169ndb3 e5 vmv0 e6 vccib0 e7 vccib0 e8 io25rsb0 fg256 pin number a3p600l function e9 io31rsb0 e10 vccib0 e11 vccib0 e12 vmv1 e13 gbc2/io62pdb1 e14 io67ppb1 e15 io64ppb1 e16 io66pdb1 f1 io166ndb3 f2 io168npb3 f3 io167ppb3 f4 io169pdb3 f5 vccib3 f6 gnd f7 vcc f8 vcc f9 vcc f10 vcc f11 gnd f12 vccib1 f13 io62ndb1 f14 io64npb1 f15 io65ppb1 f16 io66ndb1 g1 io165ndb3 g2 io165pdb3 g3 io168ppb3 g4 gfc1/io164ppb3 g5 vccib3 g6 vcc g7 gnd g8 gnd g9 gnd g10 gnd g11 vcc g12 vccib1 fg256 pin number a3p600l function
package pin assignments 4-24 revision 13 g13 gcc1/io69ppb1 g14 io65npb1 g15 io75pdb1 g16 io75ndb1 h1 gfb0/io163npb3 h2 gfa0/io162ndb3 h3 gfb1/io163ppb3 h4 vcomplf h5 gfc0/io164npb3 h6 vcc h7 gnd h8 gnd h9 gnd h10 gnd h11 vcc h12 gcc0/io69npb1 h13 gcb1/io70ppb1 h14 gca0/io71npb1 h15 io67npb1 h16 gcb0/io70npb1 j1 gfa2/io161ppb3 j2 gfa1/io162pdb3 j3 vccplf j4 io160ndb3 j5 gfb2/io160pdb3 j6 vcc j7 gnd j8 gnd j9 gnd j10 gnd j11 vcc j12 gcb2/io73ppb1 j13 gca1/io71ppb1 j14 gcc2/io74ppb1 j15 io80ppb1 j16 gca2/io72pdb1 fg256 pin number a3p600l function k1 gfc2/io159pdb3 k2 io161npb3 k3 io156ppb3 k4 io129rsb2 k5 vccib3 k6 vcc k7 gnd k8 gnd k9 gnd k10 gnd k11 vcc k12 vccib1 k13 io73npb1 k14 io80npb1 k15 io74npb1 k16 io72ndb1 l1 io159ndb3 l2 io156npb3 l3 io151ppb3 l4 io158psb3 l5 vccib3 l6 gnd l7 vcc l8 vcc l9 vcc l10 vcc l11 gnd l12 vccib1 l13 gdb0/io87npb1 l14 io85ndb1 l15 io85pdb1 l16 io84pdb1 m1 io150pdb3 m2 io151npb3 m3 io147npb3 m4 gec0/io146npb3 fg256 pin number a3p600l function m5 vmv3 m6 vccib2 m7 vccib2 m8 io117rsb2 m9 io110rsb2 m10 vccib2 m11 vccib2 m12 vmv2 m13 io94rsb2 m14 gdb1/io87ppb1 m15 gdc1/io86pdb1 m16 io84ndb1 n1 io150ndb3 n2 io147ppb3 n3 gec1/io146ppb3 n4 io140rsb2 n5 gndq n6 gea2/io143rsb2 n7 io126rsb2 n8 io120rsb2 n9 io108rsb2 n10 io103rsb2 n11 io99rsb2 n12 gndq n13 io92rsb2 n14 vjtag n15 gdc0/io86ndb1 n16 gda1/io88pdb1 p1 geb1/io145pdb3 p2 geb0/io145ndb3 p3 vmv2 p4 io138rsb2 p5 io136rsb2 p6 io131rsb2 p7 io124rsb2 p8 io119rsb2 fg256 pin number a3p600l function
proasic3l low power flash fpgas revision 13 4-25 p9 io107rsb2 p10 io104rsb2 p11 io97rsb2 p12 vmv1 p13 tck p14 vpump p15 trst p16 gda0/io88ndb1 r1 gea1/io144pdb3 r2 gea0/io144ndb3 r3 io139rsb2 r4 gec2/io141rsb2 r5 io132rsb2 r6 io127rsb2 r7 io121rsb2 r8 io114rsb2 r9 io109rsb2 r10 io105rsb2 r11 io98rsb2 r12 io96rsb2 r13 gdb2/io90rsb2 r14 tdi r15 gndq r16 tdo t1 gnd t2 io137rsb2 t3 ff/geb2/io142rsb 2 t4 io134rsb2 t5 io125rsb2 t6 io123rsb2 t7 io118rsb2 t8 io115rsb2 t9 io111rsb2 t10 io106rsb2 t11 io102rsb2 fg256 pin number a3p600l function t12 gdc2/io91rsb2 t13 io93rsb2 t14 gda2/io89rsb2 t15 tms t16 gnd fg256 pin number a3p600l function
package pin assignments 4-26 revision 13 fg256 pin number a3p1000l function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io16rsb0 a6 io22rsb0 a7 io28rsb0 a8 io35rsb0 a9 io45rsb0 a10 io50rsb0 a11 io55rsb0 a12 io61rsb0 a13 gbb1/io75rsb0 a14 gba0/io76rsb0 a15 gba1/io77rsb0 a16 gnd b1 gab2/io224pdb3 b2 gaa2/io225pdb3 b3 gndq b4 gab1/io03rsb0 b5 io17rsb0 b6 io21rsb0 b7 io27rsb0 b8 io34rsb0 b9 io44rsb0 b10 io51rsb0 b11 io57rsb0 b12 gbc1/io73rsb0 b13 gbb0/io74rsb0 b14 io71rsb0 b15 gba2/io78pdb1 b16 io81pdb1 c1 io224ndb3 c2 io225ndb3 c3 vmv3 c4 io11rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io25rsb0 c8 io36rsb0 c9 io42rsb0 c10 io49rsb0 c11 io56rsb0 c12 gbc0/io72rsb0 c13 io62rsb0 c14 vmv0 c15 io78ndb1 c16 io81ndb1 d1 io222ndb3 d2 io222pdb3 d3 gac2/io223pdb3 d4 io223ndb3 d5 gndq d6 io23rsb0 d7 io29rsb0 d8 io33rsb0 d9 io46rsb0 d10 io52rsb0 d11 io60rsb0 d12 gndq d13 io80ndb1 d14 gbb2/io79pdb1 d15 io79ndb1 d16 io82nsb1 e1 io217pdb3 e2 io218pdb3 e3 io221ndb3 e4 io221pdb3 e5 vmv0 e6 vccib0 e7 vccib0 e8 io38rsb0 fg256 pin number a3p1000l function e9 io47rsb0 e10 vccib0 e11 vccib0 e12 vmv1 e13 gbc2/io80pdb1 e14 io83ppb1 e15 io86ppb1 e16 io87pdb1 f1 io217ndb3 f2 io218ndb3 f3 io216pdb3 f4 io216ndb3 f5 vccib3 f6 gnd f7 vcc f8 vcc f9 vcc f10 vcc f11 gnd f12 vccib1 f13 io83npb1 f14 io86npb1 f15 io90ppb1 f16 io87ndb1 g1 io210psb3 g2 io213ndb3 g3 io213pdb3 g4 gfc1/io209ppb3 g5 vccib3 g6 vcc g7 gnd g8 gnd g9 gnd g10 gnd g11 vcc g12 vccib1 fg256 pin number a3p1000l function
proasic3l low power flash fpgas revision 13 4-27 g13 gcc1/io91ppb1 g14 io90npb1 g15 io88pdb1 g16 io88ndb1 h1 gfb0/io208npb3 h2 gfa0/io207ndb3 h3 gfb1/io208ppb3 h4 vcomplf h5 gfc0/io209npb3 h6 vcc h7 gnd h8 gnd h9 gnd h10 gnd h11 vcc h12 gcc0/io91npb1 h13 gcb1/io92ppb1 h14 gca0/io93npb1 h15 io96npb1 h16 gcb0/io92npb1 j1 gfa2/io206psb3 j2 gfa1/io207pdb3 j3 vccplf j4 io205ndb3 j5 gfb2/io205pdb3 j6 vcc j7 gnd j8 gnd j9 gnd j10 gnd j11 vcc j12 gcb2/io95ppb1 j13 gca1/io93ppb1 j14 gcc2/io96ppb1 j15 io100ppb1 j16 gca2/io94psb1 fg256 pin number a3p1000l function k1 gfc2/io204pdb3 k2 io204ndb3 k3 io203ndb3 k4 io203pdb3 k5 vccib3 k6 vcc k7 gnd k8 gnd k9 gnd k10 gnd k11 vcc k12 vccib1 k13 io95npb1 k14 io100npb1 k15 io102ndb1 k16 io102pdb1 l1 io202ndb3 l2 io202pdb3 l3 io196ppb3 l4 io193ppb3 l5 vccib3 l6 gnd l7 vcc l8 vcc l9 vcc l10 vcc l11 gnd l12 vccib1 l13 gdb0/io112npb1 l14 io106ndb1 l15 io106pdb1 l16 io107pdb1 m1 io197nsb3 m2 io196npb3 m3 io193npb3 m4 gec0/io190npb3 fg256 pin number a3p1000l function m5 vmv3 m6 vccib2 m7 vccib2 m8 io147rsb2 m9 io136rsb2 m10 vccib2 m11 vccib2 m12 vmv2 m13 io110ndb1 m14 gdb1/io112ppb1 m15 gdc1/io111pdb1 m16 io107ndb1 n1 io194psb3 n2 io192ppb3 n3 gec1/io190ppb3 n4 io192npb3 n5 gndq n6 gea2/io187rsb2 n7 io161rsb2 n8 io155rsb2 n9 io141rsb2 n10 io129rsb2 n11 io124rsb2 n12 gndq n13 io110pdb1 n14 vjtag n15 gdc0/io111ndb1 n16 gda1/io113pdb1 p1 geb1/io189pdb3 p2 geb0/io189ndb3 p3 vmv2 p4 io179rsb2 p5 io171rsb2 p6 io165rsb2 p7 io159rsb2 p8 io151rsb2 fg256 pin number a3p1000l function
package pin assignments 4-28 revision 13 p9 io137rsb2 p10 io134rsb2 p11 io128rsb2 p12 vmv1 p13 tck p14 vpump p15 trst p16 gda0/io113ndb1 r1 gea1/io188pdb3 r2 gea0/io188ndb3 r3 io184rsb2 r4 gec2/io185rsb2 r5 io168rsb2 r6 io163rsb2 r7 io157rsb2 r8 io149rsb2 r9 io143rsb2 r10 io138rsb2 r11 io131rsb2 r12 io125rsb2 r13 gdb2/io115rsb2 r14 tdi r15 gndq r16 tdo t1 gnd t2 io183rsb2 t3 ff/geb2/io186rsb 2 t4 io172rsb2 t5 io170rsb2 t6 io164rsb2 t7 io158rsb2 t8 io153rsb2 t9 io142rsb2 t10 io135rsb2 t11 io130rsb2 fg256 pin number a3p1000l function t12 gdc2/io116rsb2 t13 io120rsb2 t14 gda2/io114rsb2 t15 tms t16 gnd fg256 pin number a3p1000l function
proasic3l low power flash fpgas revision 13 4-29 FG324 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the bottom view of the package. 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a 17 18 u v a1 ball pad corner
package pin assignments 4-30 revision 13 FG324 pin number a3pe3000l function a1 gnd a2 io08ndb0v0 a3 io08pdb0v0 a4 io10ndb0v1 a5 io10pdb0v1 a6 io12pdb0v1 a7 gnd a8 io32ndb0v3 a9 io32pdb0v3 a10 io42ppb1v0 a11 io52npb1v1 a12 gnd a13 io66ndb1v3 a14 io72ndb1v3 a15 io72pdb1v3 a16 io74ndb1v4 a17 io74pdb1v4 a18 gnd b1 io305pdb7v3 b2 gab2/io308pdb7v4 b3 gaa0/io00npb0v0 b4 vccib0 b5 gndq b6 io12ndb0v1 b7 io18ndb0v2 b8 vccib0 b9 io42npb1v0 b10 io44ndb1v0 b11 vccib1 b12 io52ppb1v1 b13 io66pdb1v3 b14 gndq b15 vccib1 b16 gba0/io81ndb1v4 b17 gba1/io81pdb1v4 b18 io88pdb2v0 c1 io305ndb7v3 c2 io308ndb7v4 c3 gaa2/io309ppb7v4 c4 gaa1/io00ppb0v0 c5 vmv0 c6 io14ndb0v1 c7 io18pdb0v2 c8 io40ndb0v4 c9 io40pdb0v4 c10 io44pdb1v0 c11 io56ndb1v1 c12 io64ndb1v2 c13 io64pdb1v2 c14 vmv1 c15 gbc0/io79ndb1v4 c16 gbc1/io79pdb1v4 c17 gbb2/io83ppb2v0 c18 io88ndb2v0 d1 io303pdb7v3 d2 vccib7 d3 gac2/io307ppb7v4 d4 io309npb7v4 d5 gab1/io01ppb0v0 d6 io14pdb0v1 d7 io24ndb0v2 d8 io24pdb0v2 d9 io28pdb0v3 d10 io48ndb1v0 d11 io56pdb1v1 d12 io60ppb1v2 d13 gbb0/io80ndb1v4 d14 gbb1/io80pdb1v4 d15 gba2/io82pdb2v0 d16 io83npb2v0 FG324 pin number a3pe3000l function d17 vccib2 d18 io90pdb2v1 e1 io303ndb7v3 e2 gndq e2 gndq e3 vmv7 e3 vmv7 e4 io307npb7v4 e5 vccpla e6 gab0/io01npb0v0 e7 vccib0 e8 gnd e9 io28ndb0v3 e10 io48pdb1v0 e11 gnd e12 vccib1 e13 io60npb1v2 e14 vccplb e15 io82ndb2v0 e16 vmv2 e16 vmv2 e17 gndq e17 gndq e18 io90ndb2v1 f1 io299ndb7v3 f2 io299pdb7v3 f3 io295pdb7v2 f4 io295ndb7v2 f5 vcompla f6 io291ppb7v2 f7 gac0/io02ndb0v0 f8 gac1/io02pdb0v0 f9 io26pdb0v3 f10 io34pdb0v4 f11 io58ndb1v2 FG324 pin number a3pe3000l function
proasic3l low power flash fpgas revision 13 4-31 f12 io58pdb1v2 f13 io94ppb2v1 f14 vcomplb f15 gbc2/io84pdb2v0 f16 io84ndb2v0 f17 io92ndb2v1 f18 io92pdb2v1 g1 gnd g2 io287pdb7v1 g3 io287ndb7v1 g4 io283ppb7v1 g5 vccib7 g6 io279pdb7v0 g7 io291npb7v2 g8 vcc g9 io26ndb0v3 g10 io34ndb0v4 g11 vcc g12 io94npb2v1 g13 io98pdb2v2 g14 vccib2 g15 gcc0/io112npb2v3 g16 io104pdb2v2 g17 io104ndb2v2 g18 gnd h1 io267pdb6v4 h2 vccib7 h3 io283npb7v1 h4 gfb1/io274ppb7v0 h5 gnd h6 io279ndb7v0 h7 vcc h8 vcc h9 gnd h10 gnd FG324 pin number a3pe3000l function h11 vcc h12 vcc h13 io98ndb2v2 h14 gnd h15 gcb1/io113pdb2v3 h16 gcc1/io112ppb2v3 h17 vccib2 h18 io108pdb2v3 j1 io267ndb6v4 j2 gfa0/io273ndb6v4 j3 vcomplf j4 gfa2/io272pdb6v4 j5 gfb0/io274npb7v0 j6 gfc0/io275ndb7v0 j7 gfc1/io275pdb7v0 j8 gnd j9 gnd j10 gnd j11 gnd j12 gca2/io115pdb3v0 j13 gca1/io114pdb3v0 j14 gca0/io114ndb3v0 j15 gcb0/io113ndb2v3 j16 vcomplc j17 io120npb3v0 j18 io108ndb2v3 k1 io263pdb6v3 k2 gfa1/io273pdb6v4 k3 vccplf k4 io272ndb6v4 k5 gfc2/io270ppb6v4 k6 gfb2/io271pdb6v4 k7 io271ndb6v4 k8 gnd k9 gnd FG324 pin number a3pe3000l function k10 gnd k11 gnd k12 io115ndb3v0 k13 gcb2/io116pdb3v0 k14 io116ndb3v0 k15 gcc2/io117pdb3v0 k16 vccplc k17 io124npb3v1 k18 io120ppb3v0 l1 io263ndb6v3 l2 vccib6 l3 io259pdb6v3 l4 io259ndb6v3 l5 gnd l6 io270npb6v4 l7 vcc l8 vcc l9 gnd l10 gnd l11 vcc l12 vcc l13 io132pdb3v2 l14 gnd l15 io117ndb3v0 l16 io128npb3v1 l17 vccib3 l18 io124ppb3v1 m1 gnd m2 io255pdb6v2 m3 io255ndb6v2 m4 io251ppb6v2 m5 vccib6 m6 geb0/io235ndb6v0 m7 geb1/io235pdb6v0 m8 vcc FG324 pin number a3pe3000l function
package pin assignments 4-32 revision 13 m9 io192ppb4v4 m10 io154npb4v0 m11 vcc m12 gda0/io153npb3v4 m13 io132ndb3v2 m14 vccib3 m15 io134ndb3v2 m16 io134pdb3v2 m17 io128ppb3v1 m18 gnd n1 io247ndb6v1 n2 io247pdb6v1 n3 io251npb6v2 n4 gec0/io236ndb6v0 n5 vcomple n6 io212ndb5v2 n7 io212pdb5v2 n8 io192npb4v4 n9 io174pdb4v2 n10 io170pdb4v2 n11 gda2/io154ppb4v0 n12 gdb2/io155ppb4v0 n13 gda1/io153ppb3v4 n14 vcompld n15 gdb0/io152ndb3v4 n16 gdb1/io152pdb3v4 n17 io138ndb3v3 n18 io138pdb3v3 p1 io245pdb6v1 p2 gndq p2 gndq p3 vmv6 p3 vmv6 p4 gec1/io236pdb6v0 p5 vccple FG324 pin number a3pe3000l function p6 io214pdb5v2 p7 vccib5 p8 gnd p9 io174ndb4v2 p10 io170ndb4v2 p11 gnd p12 vccib4 p13 io155npb4v0 p14 vccpld p15 vjtag p16 gdc0/io151ndb3v4 p17 gdc1/io151pdb3v4 p18 io142pdb3v3 r1 io245ndb6v1 r2 vccib6 r3 gea1/io234ppb6v0 r4 io232ndb5v4 r5 ff/geb2/io232pdb5v4 r6 io214ndb5v2 r7 io202pdb5v1 r8 io194pdb5v0 r9 io186pdb4v4 r10 io178pdb4v3 r11 io168nsb4v1 r12 io164pdb4v1 r13 gdc2/io156pdb4v0 r14 tck r15 vpump r16 trst r17 vccib3 r18 io142ndb3v3 t1 io241pdb6v0 t2 gea0/io234npb6v0 t3 io233npb5v4 t4 io231npb5v4 FG324 pin number a3pe3000l function t5 vmv5 t6 io208ndb5v1 t7 io202ndb5v1 t8 io194ndb5v0 t9 io186ndb4v4 t10 io178ndb4v3 t11 io166npb4v1 t12 io164ndb4v1 t13 io156ndb4v0 t14 vmv4 t15 tdi t16 gndq t16 gndq t17 tdo t18 io146pdb3v4 u1 io241ndb6v0 u2 gea2/io233ppb5v4 u3 gec2/io231ppb5v4 u4 vccib5 u5 gndq u6 io208pdb5v1 u7 io198ppb5v0 u8 vccib5 u9 io182npb4v3 u10 io180npb4v3 u11 vccib4 u12 io166ppb4v1 u13 io162pdb4v1 u14 gndq u15 vccib4 u16 tms u17 vmv3 u17 vmv3 u18 io146ndb3v4 v1 gnd FG324 pin number a3pe3000l function
proasic3l low power flash fpgas revision 13 4-33 v2 io218ndb5v3 v3 io218pdb5v3 v4 io206ndb5v1 v5 io206pdb5v1 v6 io198npb5v0 v7 gnd v8 io190ndb4v4 v9 io190pdb4v4 v10 io182ppb4v3 v11 io180ppb4v3 v12 gnd v13 io162ndb4v1 v14 io160ndb4v0 v15 io160pdb4v0 v16 io158ndb4v0 v17 io158pdb4v0 v18 gnd FG324 pin number a3pe3000l function
package pin assignments 4-34 revision 13 fg484 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/produ cts/solutions/package/docs.aspx. note: this is the bottom view of the package. a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a1 ball pad corner
proasic3l low power flash fpgas revision 13 4-35 fg484 pin number a3p600l function a1 gnd a2 gnd a3 vccib0 a4 nc a5 nc a6 io09rsb0 a7 io15rsb0 a8 nc a9 nc a10 io22rsb0 a11 io23rsb0 a12 io29rsb0 a13 io35rsb0 a14 nc a15 nc a16 io46rsb0 a17 io48rsb0 a18 nc a19 nc a20 vccib0 a21 gnd a22 gnd aa1 gnd aa2 vccib3 aa3 nc aa4 nc aa5 nc aa6 io135rsb2 aa7 io133rsb2 aa8 nc aa9 nc aa10 nc aa11 nc aa12 nc aa13 nc aa14 nc aa15 nc aa16 io101rsb2 aa17 nc aa18 nc aa19 nc aa20 nc aa21 vccib1 aa22 gnd ab1 gnd ab2 gnd ab3 vccib2 ab4 nc ab5 nc ab6 io130rsb2 ab7 io128rsb2 ab8 io122rsb2 ab9 io116rsb2 ab10 nc ab11 nc ab12 io113rsb2 ab13 io112rsb2 ab14 nc ab15 nc ab16 io100rsb2 ab17 io95rsb2 ab18 nc ab19 nc ab20 vccib2 ab21 gnd ab22 gnd b1 gnd b2 vccib3 b3 nc b4 nc b5 nc b6 io08rsb0 fg484 pin number a3p600l function b7 io12rsb0 b8 nc b9 nc b10 io17rsb0 b11 nc b12 nc b13 io36rsb0 b14 nc b15 nc b16 io47rsb0 b17 io49rsb0 b18 nc b19 nc b20 nc b21 vccib1 b22 gnd c1 vccib3 c2 nc c3 nc c4 nc c5 gnd c6 nc c7 nc c8 vcc c9 vcc c10 nc c11 nc c12 nc c13 nc c14 vcc c15 vcc c16 nc c17 nc c18 gnd c19 nc c20 nc fg484 pin number a3p600l function
package pin assignments 4-36 revision 13 c21 nc c22 vccib1 d1 nc d2 nc d3 nc d4 gnd d5 gaa0/io00rsb0 d6 gaa1/io01rsb0 d7 gab0/io02rsb0 d8 io11rsb0 d9 io16rsb0 d10 io18rsb0 d11 io28rsb0 d12 io34rsb0 d13 io37rsb0 d14 io41rsb0 d15 io43rsb0 d16 gbb1/io57rsb0 d17 gba0/io58rsb0 d18 gba1/io59rsb0 d19 gnd d20 nc d21 nc d22 nc e1 nc e2 nc e3 gnd e4 gab2/io173pdb3 e5 gaa2/io174pdb3 e6 gndq e7 gab1/io03rsb0 e8 io13rsb0 e9 io14rsb0 e10 io21rsb0 e11 io27rsb0 e12 io32rsb0 fg484 pin number a3p600l function e13 io38rsb0 e14 io42rsb0 e15 gbc1/io55rsb0 e16 gbb0/io56rsb0 e17 io52rsb0 e18 gba2/io60pdb1 e19 io60ndb1 e20 gnd e21 nc e22 nc f1 nc f2 nc f3 nc f4 io173ndb3 f5 io174ndb3 f6 vmv3 f7 io07rsb0 f8 gac0/io04rsb0 f9 gac1/io05rsb0 f10 io20rsb0 f11 io24rsb0 f12 io33rsb0 f13 io39rsb0 f14 io44rsb0 f15 gbc0/io54rsb0 f16 io51rsb0 f17 vmv0 f18 io61npb1 f19 io63pdb1 f20 nc f21 nc f22 nc g1 io170ndb3 g2 io170pdb3 g3 nc g4 io171ndb3 fg484 pin number a3p600l function g5 io171pdb3 g6 gac2/io172pdb3 g7 io06rsb0 g8 gndq g9 io10rsb0 g10 io19rsb0 g11 io26rsb0 g12 io30rsb0 g13 io40rsb0 g14 io45rsb0 g15 gndq g16 io50rsb0 g17 gbb2/io61ppb1 g18 io53rsb0 g19 io63ndb1 g20 nc g21 nc g22 nc h1 nc h2 nc h3 vcc h4 io166pdb3 h5 io167npb3 h6 io172ndb3 h7 io169ndb3 h8 vmv0 h9 vccib0 h10 vccib0 h11 io25rsb0 h12 io31rsb0 h13 vccib0 h14 vccib0 h15 vmv1 h16 gbc2/io62pdb1 h17 io67ppb1 h18 io64ppb1 fg484 pin number a3p600l function
proasic3l low power flash fpgas revision 13 4-37 h19 io66pdb1 h20 vcc h21 nc h22 nc j1 nc j2 nc j3 nc j4 io166ndb3 j5 io168npb3 j6 io167ppb3 j7 io169pdb3 j8 vccib3 j9 gnd j10 vcc j11 vcc j12 vcc j13 vcc j14 gnd j15 vccib1 j16 io62ndb1 j17 io64npb1 j18 io65ppb1 j19 io66ndb1 j20 nc j21 io68pdb1 j22 io68ndb1 k1 io157pdb3 k2 io157ndb3 k3 nc k4 io165ndb3 k5 io165pdb3 k6 io168ppb3 k7 gfc1/io164ppb3 k8 vccib3 k9 vcc k10 gnd fg484 pin number a3p600l function k11 gnd k12 gnd k13 gnd k14 vcc k15 vccib1 k16 gcc1/io69ppb1 k17 io65npb1 k18 io75pdb1 k19 io75ndb1 k20 nc k21 io76ndb1 k22 io76pdb1 l1 nc l2 io155pdb3 l3 nc l4 gfb0/io163npb3 l5 gfa0/io162ndb3 l6 gfb1/io163ppb3 l7 vcomplf l8 gfc0/io164npb3 l9 vcc l10 gnd l11 gnd l12 gnd l13 gnd l14 vcc l15 gcc0/io69npb1 l16 gcb1/io70ppb1 l17 gca0/io71npb1 l18 io67npb1 l19 gcb0/io70npb1 l20 io77pdb1 l21 io77ndb1 l22 io78npb1 m1 nc m2 io155ndb3 fg484 pin number a3p600l function m3 io158npb3 m4 gfa2/io161ppb3 m5 gfa1/io162pdb3 m6 vccplf m7 io160ndb3 m8 gfb2/io160pdb3 m9 vcc m10 gnd m11 gnd m12 gnd m13 gnd m14 vcc m15 gcb2/io73ppb1 m16 gca1/io71ppb1 m17 gcc2/io74ppb1 m18 io80ppb1 m19 gca2/io72pdb1 m20 io79ppb1 m21 io78ppb1 m22 nc n1 io154ndb3 n2 io154pdb3 n3 nc n4 gfc2/io159pdb3 n5 io161npb3 n6 io156ppb3 n7 io129rsb2 n8 vccib3 n9 vcc n10 gnd n11 gnd n12 gnd n13 gnd n14 vcc n15 vccib1 n16 io73npb1 fg484 pin number a3p600l function
package pin assignments 4-38 revision 13 n17 io80npb1 n18 io74npb1 n19 io72ndb1 n20 nc n21 io79npb1 n22 nc p1 nc p2 io153pdb3 p3 io153ndb3 p4 io159ndb3 p5 io156npb3 p6 io151ppb3 p7 io158ppb3 p8 vccib3 p9 gnd p10 vcc p11 vcc p12 vcc p13 vcc p14 gnd p15 vccib1 p16 gdb0/io87npb1 p17 io85ndb1 p18 io85pdb1 p19 io84pdb1 p20 nc p21 io81pdb1 p22 nc r1 nc r2 nc r3 vcc r4 io150pdb3 r5 io151npb3 r6 io147npb3 r7 gec0/io146npb3 r8 vmv3 fg484 pin number a3p600l function r9 vccib2 r10 vccib2 r11 io117rsb2 r12 io110rsb2 r13 vccib2 r14 vccib2 r15 vmv2 r16 io94rsb2 r17 gdb1/io87ppb1 r18 gdc1/io86pdb1 r19 io84ndb1 r20 vcc r21 io81ndb1 r22 io82pdb1 t1 io152pdb3 t2 io152ndb3 t3 nc t4 io150ndb3 t5 io147ppb3 t6 gec1/io146ppb3 t7 io140rsb2 t8 gndq t9 gea2/io143rsb2 t10 io126rsb2 t11 io120rsb2 t12 io108rsb2 t13 io103rsb2 t14 io99rsb2 t15 gndq t16 io92rsb2 t17 vjtag t18 gdc0/io86ndb1 t19 gda1/io88pdb1 t20 nc t21 io83pdb1 t22 io82ndb1 fg484 pin number a3p600l function u1 io149pdb3 u2 io149ndb3 u3 nc u4 geb1/io145pdb3 u5 geb0/io145ndb3 u6 vmv2 u7 io138rsb2 u8 io136rsb2 u9 io131rsb2 u10 io124rsb2 u11 io119rsb2 u12 io107rsb2 u13 io104rsb2 u14 io97rsb2 u15 vmv1 u16 tck u17 vpump u18 trst u19 gda0/io88ndb1 u20 nc u21 io83ndb1 u22 nc v1 nc v2 nc v3 gnd v4 gea1/io144pdb3 v5 gea0/io144ndb3 v6 io139rsb2 v7 gec2/io141rsb2 v8 io132rsb2 v9 io127rsb2 v10 io121rsb2 v11 io114rsb2 v12 io109rsb2 v13 io105rsb2 v14 io98rsb2 fg484 pin number a3p600l function
proasic3l low power flash fpgas revision 13 4-39 v15 io96rsb2 v16 gdb2/io90rsb2 v17 tdi v18 gndq v19 tdo v20 gnd v21 nc v22 nc w1 nc w2 io148pdb3 w3 nc w4 gnd w5 io137rsb2 w6 ff/geb2/io142rsb2 w7 io134rsb2 w8 io125rsb2 w9 io123rsb2 w10 io118rsb2 w11 io115rsb2 w12 io111rsb2 w13 io106rsb2 w14 io102rsb2 w15 gdc2/io91rsb2 w16 io93rsb2 w17 gda2/io89rsb2 w18 tms w19 gnd w20 nc w21 nc w22 nc y1 vccib3 y2 io148ndb3 y3 nc y4 nc y5 gnd y6 nc fg484 pin number a3p600l function y7 nc y8 vcc y9 vcc y10 nc y11 nc y12 nc y13 nc y14 vcc y15 vcc y16 nc y17 nc y18 gnd y19 nc y20 nc y21 nc y22 vccib1 fg484 pin number a3p600l function
package pin assignments 4-40 revision 13 fg484 pin number a3p1000l function a1 gnd a2 gnd a3 vccib0 a4 io07rsb0 a5 io09rsb0 a6 io13rsb0 a7 io18rsb0 a8 io20rsb0 a9 io26rsb0 a10 io32rsb0 a11 io40rsb0 a12 io41rsb0 a13 io53rsb0 a14 io59rsb0 a15 io64rsb0 a16 io65rsb0 a17 io67rsb0 a18 io69rsb0 a19 nc a20 vccib0 a21 gnd a22 gnd aa1 gnd aa2 vccib3 aa3 nc aa4 io181rsb2 aa5 io178rsb2 aa6 io175rsb2 aa7 io169rsb2 aa8 io166rsb2 aa9 io160rsb2 aa10 io152rsb2 aa11 io146rsb2 aa12 io139rsb2 aa13 io133rsb2 aa14 nc aa15 nc aa16 io122rsb2 aa17 io119rsb2 aa18 io117rsb2 aa19 nc aa20 nc aa21 vccib1 aa22 gnd ab1 gnd ab2 gnd ab3 vccib2 ab4 io180rsb2 ab5 io176rsb2 ab6 io173rsb2 ab7 io167rsb2 ab8 io162rsb2 ab9 io156rsb2 ab10 io150rsb2 ab11 io145rsb2 ab12 io144rsb2 ab13 io132rsb2 ab14 io127rsb2 ab15 io126rsb2 ab16 io123rsb2 ab17 io121rsb2 ab18 io118rsb2 ab19 nc ab20 vccib2 ab21 gnd ab22 gnd b1 gnd b2 vccib3 b3 nc b4 io06rsb0 b5 io08rsb0 b6 io12rsb0 fg484 pin number a3p1000l function b7 io15rsb0 b8 io19rsb0 b9 io24rsb0 b10 io31rsb0 b11 io39rsb0 b12 io48rsb0 b13 io54rsb0 b14 io58rsb0 b15 io63rsb0 b16 io66rsb0 b17 io68rsb0 b18 io70rsb0 b19 nc b20 nc b21 vccib1 b22 gnd c1 vccib3 c2 io220pdb3 c3 nc c4 nc c5 gnd c6 io10rsb0 c7 io14rsb0 c8 vcc c9 vcc c10 io30rsb0 c11 io37rsb0 c12 io43rsb0 c13 nc c14 vcc c15 vcc c16 nc c17 nc c18 gnd c19 nc c20 nc fg484 pin number a3p1000l function
proasic3l low power flash fpgas revision 13 4-41 c21 nc c22 vccib1 d1 io219pdb3 d2 io220ndb3 d3 nc d4 gnd d5 gaa0/io00rsb0 d6 gaa1/io01rsb0 d7 gab0/io02rsb0 d8 io16rsb0 d9 io22rsb0 d10 io28rsb0 d11 io35rsb0 d12 io45rsb0 d13 io50rsb0 d14 io55rsb0 d15 io61rsb0 d16 gbb1/io75rsb0 d17 gba0/io76rsb0 d18 gba1/io77rsb0 d19 gnd d20 nc d21 nc d22 nc e1 io219ndb3 e2 nc e3 gnd e4 gab2/io224pdb3 e5 gaa2/io225pdb3 e6 gndq e7 gab1/io03rsb0 e8 io17rsb0 e9 io21rsb0 e10 io27rsb0 e11 io34rsb0 e12 io44rsb0 fg484 pin number a3p1000l function e13 io51rsb0 e14 io57rsb0 e15 gbc1/io73rsb0 e16 gbb0/io74rsb0 e17 io71rsb0 e18 gba2/io78pdb1 e19 io81pdb1 e20 gnd e21 nc e22 io84pdb1 f1 nc f2 io215pdb3 f3 io215ndb3 f4 io224ndb3 f5 io225ndb3 f6 vmv3 f7 io11rsb0 f8 gac0/io04rsb0 f9 gac1/io05rsb0 f10 io25rsb0 f11 io36rsb0 f12 io42rsb0 f13 io49rsb0 f14 io56rsb0 f15 gbc0/io72rsb0 f16 io62rsb0 f17 vmv0 f18 io78ndb1 f19 io81ndb1 f20 io82ppb1 f21 nc f22 io84ndb1 g1 io214ndb3 g2 io214pdb3 g3 nc g4 io222ndb3 fg484 pin number a3p1000l function g5 io222pdb3 g6 gac2/io223pdb3 g7 io223ndb3 g8 gndq g9 io23rsb0 g10 io29rsb0 g11 io33rsb0 g12 io46rsb0 g13 io52rsb0 g14 io60rsb0 g15 gndq g16 io80ndb1 g17 gbb2/io79pdb1 g18 io79ndb1 g19 io82npb1 g20 io85pdb1 g21 io85ndb1 g22 nc h1 nc h2 nc h3 vcc h4 io217pdb3 h5 io218pdb3 h6 io221ndb3 h7 io221pdb3 h8 vmv0 h9 vccib0 h10 vccib0 h11 io38rsb0 h12 io47rsb0 h13 vccib0 h14 vccib0 h15 vmv1 h16 gbc2/io80pdb1 h17 io83ppb1 h18 io86ppb1 fg484 pin number a3p1000l function
package pin assignments 4-42 revision 13 h19 io87pdb1 h20 vcc h21 nc h22 nc j1 io212ndb3 j2 io212pdb3 j3 nc j4 io217ndb3 j5 io218ndb3 j6 io216pdb3 j7 io216ndb3 j8 vccib3 j9 gnd j10 vcc j11 vcc j12 vcc j13 vcc j14 gnd j15 vccib1 j16 io83npb1 j17 io86npb1 j18 io90ppb1 j19 io87ndb1 j20 nc j21 io89pdb1 j22 io89ndb1 k1 io211pdb3 k2 io211ndb3 k3 nc k4 io210ppb3 k5 io213ndb3 k6 io213pdb3 k7 gfc1/io209ppb3 k8 vccib3 k9 vcc k10 gnd fg484 pin number a3p1000l function k11 gnd k12 gnd k13 gnd k14 vcc k15 vccib1 k16 gcc1/io91ppb1 k17 io90npb1 k18 io88pdb1 k19 io88ndb1 k20 io94npb1 k21 io98ndb1 k22 io98pdb1 l1 nc l2 io200pdb3 l3 io210npb3 l4 gfb0/io208npb3 l5 gfa0/io207ndb3 l6 gfb1/io208ppb3 l7 vcomplf l8 gfc0/io209npb3 l9 vcc l10 gnd l11 gnd l12 gnd l13 gnd l14 vcc l15 gcc0/io91npb1 l16 gcb1/io92ppb1 l17 gca0/io93npb1 l18 io96npb1 l19 gcb0/io92npb1 l20 io97pdb1 l21 io97ndb1 l22 io99npb1 m1 nc m2 io200ndb3 fg484 pin number a3p1000l function m3 io206ndb3 m4 gfa2/io206pdb3 m5 gfa1/io207pdb3 m6 vccplf m7 io205ndb3 m8 gfb2/io205pdb3 m9 vcc m10 gnd m11 gnd m12 gnd m13 gnd m14 vcc m15 gcb2/io95ppb1 m16 gca1/io93ppb1 m17 gcc2/io96ppb1 m18 io100ppb1 m19 gca2/io94ppb1 m20 io101ppb1 m21 io99ppb1 m22 nc n1 io201ndb3 n2 io201pdb3 n3 nc n4 gfc2/io204pdb3 n5 io204ndb3 n6 io203ndb3 n7 io203pdb3 n8 vccib3 n9 vcc n10 gnd n11 gnd n12 gnd n13 gnd n14 vcc n15 vccib1 n16 io95npb1 fg484 pin number a3p1000l function
proasic3l low power flash fpgas revision 13 4-43 n17 io100npb1 n18 io102ndb1 n19 io102pdb1 n20 nc n21 io101npb1 n22 io103pdb1 p1 nc p2 io199pdb3 p3 io199ndb3 p4 io202ndb3 p5 io202pdb3 p6 io196ppb3 p7 io193ppb3 p8 vccib3 p9 gnd p10 vcc p11 vcc p12 vcc p13 vcc p14 gnd p15 vccib1 p16 gdb0/io112npb1 p17 io106ndb1 p18 io106pdb1 p19 io107pdb1 p20 nc p21 io104pdb1 p22 io103ndb1 r1 nc r2 io197ppb3 r3 vcc r4 io197npb3 r5 io196npb3 r6 io193npb3 r7 gec0/io190npb3 r8 vmv3 fg484 pin number a3p1000l function r9 vccib2 r10 vccib2 r11 io147rsb2 r12 io136rsb2 r13 vccib2 r14 vccib2 r15 vmv2 r16 io110ndb1 r17 gdb1/io112ppb1 r18 gdc1/io111pdb1 r19 io107ndb1 r20 vcc r21 io104ndb1 r22 io105pdb1 t1 io198pdb3 t2 io198ndb3 t3 nc t4 io194ppb3 t5 io192ppb3 t6 gec1/io190ppb3 t7 io192npb3 t8 gndq t9 gea2/io187rsb2 t10 io161rsb2 t11 io155rsb2 t12 io141rsb2 t13 io129rsb2 t14 io124rsb2 t15 gndq t16 io110pdb1 t17 vjtag t18 gdc0/io111ndb1 t19 gda1/io113pdb1 t20 nc t21 io108pdb1 t22 io105ndb1 fg484 pin number a3p1000l function u1 io195pdb3 u2 io195ndb3 u3 io194npb3 u4 geb1/io189pdb3 u5 geb0/io189ndb3 u6 vmv2 u7 io179rsb2 u8 io171rsb2 u9 io165rsb2 u10 io159rsb2 u11 io151rsb2 u12 io137rsb2 u13 io134rsb2 u14 io128rsb2 u15 vmv1 u16 tck u17 vpump u18 trst u19 gda0/io113ndb1 u20 nc u21 io108ndb1 u22 io109pdb1 v1 nc v2 nc v3 gnd v4 gea1/io188pdb3 v5 gea0/io188ndb3 v6 io184rsb2 v7 gec2/io185rsb2 v8 io168rsb2 v9 io163rsb2 v10 io157rsb2 v11 io149rsb2 v12 io143rsb2 v13 io138rsb2 v14 io131rsb2 fg484 pin number a3p1000l function
package pin assignments 4-44 revision 13 v15 io125rsb2 v16 gdb2/io115rsb2 v17 tdi v18 gndq v19 tdo v20 gnd v21 nc v22 io109ndb1 w1 nc w2 io191pdb3 w3 nc w4 gnd w5 io183rsb2 w6 ff/geb2/io186rsb2 w7 io172rsb2 w8 io170rsb2 w9 io164rsb2 w10 io158rsb2 w11 io153rsb2 w12 io142rsb2 w13 io135rsb2 w14 io130rsb2 w15 gdc2/io116rsb2 w16 io120rsb2 w17 gda2/io114rsb2 w18 tms w19 gnd w20 nc w21 nc w22 nc y1 vccib3 y2 io191ndb3 y3 nc y4 io182rsb2 y5 gnd y6 io177rsb2 fg484 pin number a3p1000l function y7 io174rsb2 y8 vcc y9 vcc y10 io154rsb2 y11 io148rsb2 y12 io140rsb2 y13 nc y14 vcc y15 vcc y16 nc y17 nc y18 gnd y19 nc y20 nc y21 nc y22 vccib1 fg484 pin number a3p1000l function
proasic3l low power flash fpgas revision 13 4-45 fg484 pin number a3pe3000l function a1 gnd a2 gnd a3 vccib0 a4 io10ndb0v1 a5 io10pdb0v1 a6 io16ndb0v1 a7 io16pdb0v1 a8 io18pdb0v2 a9 io24pdb0v2 a10 io28ndb0v3 a11 io28pdb0v3 a12 io46pdb1v0 a13 io54pdb1v1 a14 io56ndb1v1 a15 io56pdb1v1 a16 io64ndb1v2 a17 io64pdb1v2 a18 io72ndb1v3 a19 io74ndb1v4 a20 vccib1 a21 gnd a22 gnd aa1 gnd aa2 vccib6 aa3 io228pdb5v4 aa4 io224pdb5v3 aa5 io218ndb5v3 aa6 io218pdb5v3 aa7 io212ndb5v2 aa8 io212pdb5v2 aa9 io198pdb5v0 aa10 io198ndb5v0 aa11 io188ppb4v4 aa12 io180ndb4v3 aa13 io180pdb4v3 aa14 io170ndb4v2 aa15 io170pdb4v2 aa16 io166ndb4v1 aa17 io166pdb4v1 aa18 io160ndb4v0 aa19 io160pdb4v0 aa20 io158npb4v0 aa21 vccib3 aa22 gnd ab1 gnd ab2 gnd ab3 vccib5 ab4 io216ndb5v2 ab5 io216pdb5v2 ab6 io210ndb5v2 ab7 io210pdb5v2 ab8 io208ndb5v1 ab9 io208pdb5v1 ab10 io197ndb5v0 ab11 io197pdb5v0 ab12 io174ndb4v2 ab13 io174pdb4v2 ab14 io172ndb4v2 ab15 io172pdb4v2 ab16 io168ndb4v1 ab17 io168pdb4v1 ab18 io162ndb4v1 ab19 io162pdb4v1 ab20 vccib4 ab21 gnd ab22 gnd b1 gnd b2 vccib7 b3 io06ppb0v0 b4 io08ndb0v0 fg484 pin number a3pe3000l function b5 io08pdb0v0 b6 io14ndb0v1 b7 io14pdb0v1 b8 io18ndb0v2 b9 io24ndb0v2 b10 io34pdb0v4 b11 io40pdb0v4 b12 io46ndb1v0 b13 io54ndb1v1 b14 io62ndb1v2 b15 io62pdb1v2 b16 io68ndb1v3 b17 io68pdb1v3 b18 io72pdb1v3 b19 io74pdb1v4 b20 io76npb1v4 b21 vccib2 b22 gnd c1 vccib7 c2 io303pdb7v3 c3 io305pdb7v3 c4 io06npb0v0 c5 gnd c6 io12ndb0v1 c7 io12pdb0v1 c8 vcc c9 vcc c10 io34ndb0v4 c11 io40ndb0v4 c12 io48ndb1v0 c13 io48pdb1v0 c14 vcc c15 vcc c16 io70ndb1v3 c17 io70pdb1v3 fg484 pin number a3pe3000l function
package pin assignments 4-46 revision 13 c18 gnd c19 io76ppb1v4 c20 io88ndb2v0 c21 io94ppb2v1 c22 vccib2 d1 io293pdb7v2 d2 io303ndb7v3 d3 io305ndb7v3 d4 gnd d5 gaa0/io00ndb0v0 d6 gaa1/io00pdb0v0 d7 gab0/io01ndb0v0 d8 io20pdb0v2 d9 io22pdb0v2 d10 io30pdb0v3 d11 io38ndb0v4 d12 io52ndb1v1 d13 io52pdb1v1 d14 io66ndb1v3 d15 io66pdb1v3 d16 gbb1/io80pdb1v4 d17 gba0/io81ndb1v4 d18 gba1/io81pdb1v4 d19 gnd d20 io88pdb2v0 d21 io90pdb2v1 d22 io94npb2v1 e1 io293ndb7v2 e2 io299ppb7v3 e3 gnd e4 gab2/io308pdb7v4 e5 gaa2/io309pdb7v4 e6 gndq e7 gab1/io01pdb0v0 e8 io20ndb0v2 fg484 pin number a3pe3000l function e9 io22ndb0v2 e10 io30ndb0v3 e11 io38pdb0v4 e12 io44ndb1v0 e13 io58ndb1v2 e14 io58pdb1v2 e15 gbc1/io79pdb1v4 e16 gbb0/io80ndb1v4 e17 gndq e18 gba2/io82pdb2v0 e19 io86ndb2v0 e20 gnd e21 io90ndb2v1 e22 io98pdb2v2 f1 io299npb7v3 f2 io301ndb7v3 f3 io301pdb7v3 f4 io308ndb7v4 f5 io309ndb7v4 f6 vmv7 f7 vccpla f8 gac0/io02ndb0v0 f9 gac1/io02pdb0v0 f10 io32ndb0v3 f11 io32pdb0v3 f12 io44pdb1v0 f13 io50ndb1v1 f14 io60pdb1v2 f15 gbc0/io79ndb1v4 f16 vccplb f17 vmv2 f18 io82ndb2v0 f19 io86pdb2v0 f20 io96pdb2v1 f21 io96ndb2v1 fg484 pin number a3pe3000l function f22 io98ndb2v2 g1 io289ndb7v1 g2 io289pdb7v1 g3 io291ppb7v2 g4 io295pdb7v2 g5 io297pdb7v2 g6 gac2/io307pdb7v4 g7 vcompla g8 gndq g9 io26ndb0v3 g10 io26pdb0v3 g11 io36pdb0v4 g12 io42pdb1v0 g13 io50pdb1v1 g14 io60ndb1v2 g15 gndq g16 vcomplb g17 gbb2/io83pdb2v0 g18 io92pdb2v1 g19 io92ndb2v1 g20 io102pdb2v2 g21 io102ndb2v2 g22 io105ndb2v2 h1 io286psb7v1 h2 io291npb7v2 h3 vcc h4 io295ndb7v2 h5 io297ndb7v2 h6 io307ndb7v4 h7 io287pdb7v1 h8 vmv0 h9 vccib0 h10 vccib0 h11 io36ndb0v4 h12 io42ndb1v0 fg484 pin number a3pe3000l function
proasic3l low power flash fpgas revision 13 4-47 h13 vccib1 h14 vccib1 h15 vmv1 h16 gbc2/io84pdb2v0 h17 io83ndb2v0 h18 io100ndb2v2 h19 io100pdb2v2 h20 vcc h21 vmv2 h22 io105pdb2v2 j1 io285ndb7v1 j2 io285pdb7v1 j3 vmv7 j4 io279pdb7v0 j5 io283pdb7v1 j6 io281pdb7v0 j7 io287ndb7v1 j8 vccib7 j9 gnd j10 vcc j11 vcc j12 vcc j13 vcc j14 gnd j15 vccib2 j16 io84ndb2v0 j17 io104ndb2v2 j18 io104pdb2v2 j19 io106ppb2v3 j20 gndq j21 io109pdb2v3 j22 io107pdb2v3 k1 io277ndb7v0 k2 io277pdb7v0 k3 gndq fg484 pin number a3pe3000l function k4 io279ndb7v0 k5 io283ndb7v1 k6 io281ndb7v0 k7 gfc1/io275ppb7v0 k8 vccib7 k9 vcc k10 gnd k11 gnd k12 gnd k13 gnd k14 vcc k15 vccib2 k16 gcc1/io112ppb2v3 k17 io108ndb2v3 k18 io108pdb2v3 k19 io110npb2v3 k20 io106npb2v3 k21 io109ndb2v3 k22 io107ndb2v3 l1 io257psb6v2 l2 io276pdb7v0 l3 io276ndb7v0 l4 gfb0/io274npb7v0 l5 gfa0/io273ndb6v4 l6 gfb1/io274ppb7v0 l7 vcomplf l8 gfc0/io275npb7v0 l9 vcc l10 gnd l11 gnd l12 gnd l13 gnd l14 vcc l15 gcc0/io112npb2v3 l16 gcb1/io113ppb2v3 fg484 pin number a3pe3000l function l17 gca0/io114npb3v0 l18 vcomplc l19 gcb0/io113npb2v3 l20 io110ppb2v3 l21 io111ndb2v3 l22 io111pdb2v3 m1 gndq m2 io255npb6v2 m3 io272ndb6v4 m4 gfa2/io272pdb6v4 m5 gfa1/io273pdb6v4 m6 vccplf m7 io271ndb6v4 m8 gfb2/io271pdb6v4 m9 vcc m10 gnd m11 gnd m12 gnd m13 gnd m14 vcc m15 gcb2/io116ppb3v0 m16 gca1/io114ppb3v0 m17 gcc2/io117ppb3v0 m18 vccplc m19 gca2/io115pdb3v0 m20 io115ndb3v0 m21 io126pdb3v1 m22 io124psb3v1 n1 io255ppb6v2 n2 io253ndb6v2 n3 vmv6 n4 gfc2/io270ppb6v4 n5 io261ppb6v3 n6 io263pdb6v3 n7 io263ndb6v3 fg484 pin number a3pe3000l function
package pin assignments 4-48 revision 13 n8 vccib6 n9 vcc n10 gnd n11 gnd n12 gnd n13 gnd n14 vcc n15 vccib3 n16 io116npb3v0 n17 io132npb3v2 n18 io117npb3v0 n19 io132ppb3v2 n20 gndq n21 io126ndb3v1 n22 io128pdb3v1 p1 io247pdb6v1 p2 io253pdb6v2 p3 io270npb6v4 p4 io261npb6v3 p5 io249ppb6v1 p6 io259pdb6v3 p7 io259ndb6v3 p8 vccib6 p9 gnd p10 vcc p11 vcc p12 vcc p13 vcc p14 gnd p15 vccib3 p16 gdb0/io152npb3v4 p17 io136ndb3v2 p18 io136pdb3v2 p19 io138pdb3v3 p20 vmv3 fg484 pin number a3pe3000l function p21 io130pdb3v2 p22 io128ndb3v1 r1 io247ndb6v1 r2 io245pdb6v1 r3 vcc r4 io249npb6v1 r5 io251ndb6v2 r6 io251pdb6v2 r7 gec0/io236npb6v0 r8 vmv5 r9 vccib5 r10 vccib5 r11 io196ndb5v0 r12 io196pdb5v0 r13 vccib4 r14 vccib4 r15 vmv3 r16 vccpld r17 gdb1/io152ppb3v4 r18 gdc1/io151pdb3v4 r19 io138ndb3v3 r20 vcc r21 io130ndb3v2 r22 io134pdb3v2 t1 io243ppb6v1 t2 io245ndb6v1 t3 io243npb6v1 t4 io241pdb6v0 t5 io241ndb6v0 t6 gec1/io236ppb6v0 t7 vcomple t8 gndq t9 gea2/io233ppb5v4 t10 io206ndb5v1 t11 io202ndb5v1 fg484 pin number a3pe3000l function t12 io194ndb5v0 t13 io186ndb4v4 t14 io186pdb4v4 t15 gndq t16 vcompld t17 vjtag t18 gdc0/io151ndb3v4 t19 gda1/io153pdb3v4 t20 io144pdb3v3 t21 io140pdb3v3 t22 io134ndb3v2 u1 io240ppb6v0 u2 io238pdb6v0 u3 io238ndb6v0 u4 geb1/io235pdb6v0 u5 geb0/io235ndb6v0 u6 vmv6 u7 vccple u8 io233npb5v4 u9 io222ppb5v3 u10 io206pdb5v1 u11 io202pdb5v1 u12 io194pdb5v0 u13 io176ndb4v2 u14 io176pdb4v2 u15 vmv4 u16 tck u17 vpump u18 trst u19 gda0/io153ndb3v4 u20 io144ndb3v3 u21 io140ndb3v3 u22 io142pdb3v3 v1 io239pdb6v0 v2 io240npb6v0 fg484 pin number a3pe3000l function
proasic3l low power flash fpgas revision 13 4-49 v3 gnd v4 gea1/io234pdb6v0 v5 gea0/io234ndb6v0 v6 gndq v7 gec2/io231pdb5v4 v8 io222npb5v3 v9 io204ndb5v1 v10 io204pdb5v1 v11 io195ndb5v0 v12 io195pdb5v0 v13 io178ndb4v3 v14 io178pdb4v3 v15 io155ndb4v0 v16 gdb2/io155pdb4v0 v17 tdi v18 gndq v19 tdo v20 gnd v21 io146pdb3v4 v22 io142ndb3v3 w1 io239ndb6v0 w2 io237pdb6v0 w3 io230psb5v4 w4 gnd w5 io232ndb5v4 w6 ff/geb2/io232pdb5v4 w7 io231ndb5v4 w8 io214ndb5v2 w9 io214pdb5v2 w10 io200ndb5v0 w11 io192ndb4v4 w12 io184ndb4v3 w13 io184pdb4v3 w14 io156ndb4v0 w15 gdc2/io156pdb4v0 fg484 pin number a3pe3000l function w16 io154ndb4v0 w17 gda2/io154pdb4v0 w18 tms w19 gnd w20 io150ndb3v4 w21 io146ndb3v4 w22 io148ppb3v4 y1 vccib6 y2 io237ndb6v0 y3 io228ndb5v4 y4 io224ndb5v3 y5 gnd y6 io220ndb5v3 y7 io220pdb5v3 y8 vcc y9 vcc y10 io200pdb5v0 y11 io192pdb4v4 y12 io188npb4v4 y13 io187psb4v4 y14 vcc y15 vcc y16 io164ndb4v1 y17 io164pdb4v1 y18 gnd y19 io158ppb4v0 y20 io150pdb3v4 y21 io148npb3v4 y22 vccib3 fg484 pin number a3pe3000l function
package pin assignments 4-50 revision 13 fg896 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the bottom view. a1 ball pad corner a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ag ah aj ak
proasic3l low power flash fpgas revision 13 4-51 fg896 pin number a3pe3000l function a2 gnd a3 gnd a4 io14npb0v1 a5 gnd a6 io07npb0v0 a7 gnd a8 io09ndb0v1 a9 io17ndb0v2 a10 io17pdb0v2 a11 io21ndb0v2 a12 io21pdb0v2 a13 io33ndb0v4 a14 io33pdb0v4 a15 io35ndb0v4 a16 io35pdb0v4 a17 io41ndb1v0 a18 io43ndb1v0 a19 io43pdb1v0 a20 io45ndb1v0 a21 io45pdb1v0 a22 io57ndb1v2 a23 io57pdb1v2 a24 gnd a25 io69ppb1v3 a26 gnd a27 gbc1/io79ppb1v4 a28 gnd a29 gnd aa1 io256pdb6v2 aa2 io248pdb6v1 aa3 io248ndb6v1 aa4 io246ndb6v1 aa5 gea1/io234pdb6v0 aa6 gea0/io234ndb6v0 aa7 io243ppb6v1 aa8 io245ndb6v1 aa9 geb1/io235ppb6v0 aa10 vcc aa11 io226ppb5v4 aa12 vccib5 aa13 vccib5 aa14 vccib5 aa15 vccib5 aa16 vccib4 aa17 vccib4 aa18 vccib4 aa19 vccib4 aa20 io174pdb4v2 aa21 vcc aa22 io142npb3v3 aa23 io144ndb3v3 aa24 io144pdb3v3 aa25 io146ndb3v4 aa26 io146pdb3v4 aa27 io147pdb3v4 aa28 io139ndb3v3 aa29 io139pdb3v3 aa30 io133ndb3v2 ab1 io256ndb6v2 ab2 io244pdb6v1 ab3 io244ndb6v1 ab4 io241pdb6v0 ab5 io241ndb6v0 ab6 io243npb6v1 ab7 vccib6 ab8 vccple ab9 vcc ab10 io222pdb5v3 ab11 io218ppb5v3 ab12 io206ndb5v1 fg896 pin number a3pe3000l function ab13 io206pdb5v1 ab14 io198ndb5v0 ab15 io198pdb5v0 ab16 io192ndb4v4 ab17 io192pdb4v4 ab18 io178ndb4v3 ab19 io178pdb4v3 ab20 io174ndb4v2 ab21 io162npb4v1 ab22 vcc ab23 vccpld ab24 vccib3 ab25 io150pdb3v4 ab26 io148pdb3v4 ab27 io147ndb3v4 ab28 io145pdb3v3 ab29 io143pdb3v3 ab30 io137pdb3v2 ac1 io254pdb6v2 ac2 io254ndb6v2 ac3 io240pdb6v0 ac4 gec1/io236pdb6v0 ac5 io237pdb6v0 ac6 io237ndb6v0 ac7 vcomple ac8 gnd ac9 io226npb5v4 ac10 io222ndb5v3 ac11 io216npb5v2 ac12 io210npb5v2 ac13 io204ndb5v1 ac14 io204pdb5v1 ac15 io194ndb5v0 ac16 io188ndb4v4 ac17 io188pdb4v4 fg896 pin number a3pe3000l function
package pin assignments 4-52 revision 13 ac18 io182ppb4v3 ac19 io170npb4v2 ac20 io164ndb4v1 ac21 io164pdb4v1 ac22 io162ppb4v1 ac23 gnd ac24 vcompld ac25 io150ndb3v4 ac26 io148ndb3v4 ac27 gda1/io153pdb3v4 ac28 io145ndb3v3 ac29 io143ndb3v3 ac30 io137ndb3v2 ad1 gnd ad2 io242npb6v1 ad3 io240ndb6v0 ad4 gec0/io236ndb6v0 ad5 vccib6 ad6 gndq ad6 gndq ad7 vcc ad8 vmv5 ad9 vccib5 ad10 io224ppb5v3 ad11 io218npb5v3 ad12 io216ppb5v2 ad13 io210ppb5v2 ad14 io202ppb5v1 ad15 io194pdb5v0 ad16 io190pdb4v4 ad17 io182npb4v3 ad18 io176ndb4v2 ad19 io176pdb4v2 ad20 io170ppb4v2 ad21 io166pdb4v1 fg896 pin number a3pe3000l function ad22 vccib4 ad23 tck ad24 vcc ad25 trst ad26 vccib3 ad27 gda0/io153ndb3v4 ad28 gdc0/io151ndb3v4 ad29 gdc1/io151pdb3v4 ad30 gnd ae1 io242ppb6v1 ae2 vcc ae3 io239pdb6v0 ae4 io239ndb6v0 ae5 vmv6 ae5 vmv6 ae6 gnd ae7 gndq ae8 io230ndb5v4 ae9 io224npb5v3 ae10 io214npb5v2 ae11 io212ndb5v2 ae12 io212pdb5v2 ae13 io202npb5v1 ae14 io200ndb5v0 ae15 io196pdb5v0 ae16 io190ndb4v4 ae17 io184pdb4v3 ae18 io184ndb4v3 ae19 io172pdb4v2 ae20 io172ndb4v2 ae21 io166ndb4v1 ae22 io160pdb4v0 ae23 gndq ae24 vmv4 ae25 gnd fg896 pin number a3pe3000l function ae26 gdb0/io152ndb3v4 ae27 gdb1/io152pdb3v4 ae28 vmv3 ae28 vmv3 ae29 vcc ae30 io149pdb3v4 af1 gnd af2 io238ppb6v0 af3 vccib6 af4 io220npb5v3 af5 vcc af6 io228ndb5v4 af7 vccib5 af8 io230pdb5v4 af9 io229ndb5v4 af10 io229pdb5v4 af11 io214ppb5v2 af12 io208ndb5v1 af13 io208pdb5v1 af14 io200pdb5v0 af15 io196ndb5v0 af16 io186ndb4v4 af17 io186pdb4v4 af18 io180ndb4v3 af19 io180pdb4v3 af20 io168ndb4v1 af21 io168pdb4v1 af22 io160ndb4v0 af23 io158npb4v0 af24 vccib4 af25 io154npb4v0 af26 vcc af27 tdo af28 vccib3 af29 gndq fg896 pin number a3pe3000l function
proasic3l low power flash fpgas revision 13 4-53 af29 gndq af30 gnd ag1 io238npb6v0 ag2 vcc ag3 io232npb5v4 ag4 gnd ag5 io220ppb5v3 ag6 io228pdb5v4 ag7 io231ndb5v4 ag8 gec2/io231pdb5v4 ag9 io225npb5v3 ag10 io223npb5v3 ag11 io221pdb5v3 ag12 io221ndb5v3 ag13 io205npb5v1 ag14 io199ndb5v0 ag15 io199pdb5v0 ag16 io187ndb4v4 ag17 io187pdb4v4 ag18 io181ndb4v3 ag19 io171ppb4v2 ag20 io165npb4v1 ag21 io161npb4v0 ag22 io159ndb4v0 ag23 io159pdb4v0 ag24 io158ppb4v0 ag25 gdb2/io155pdb4v0 ag26 gda2/io154ppb4v0 ag27 gnd ag28 vjtag ag29 vcc ag30 io149ndb3v4 ah1 gnd ah2 io233npb5v4 ah3 vcc fg896 pin number a3pe3000l function ah4 ff/geb2/io232ppb5v4 ah5 vccib5 ah6 io219ndb5v3 ah7 io219pdb5v3 ah8 io227ndb5v4 ah9 io227pdb5v4 ah10 io225ppb5v3 ah11 io223ppb5v3 ah12 io211ndb5v2 ah13 io211pdb5v2 ah14 io205ppb5v1 ah15 io195ndb5v0 ah16 io185ndb4v3 ah17 io185pdb4v3 ah18 io181pdb4v3 ah19 io177ndb4v2 ah20 io171npb4v2 ah21 io165ppb4v1 ah22 io161ppb4v0 ah23 io157ndb4v0 ah24 io157pdb4v0 ah25 io155ndb4v0 ah26 vccib4 ah27 tdi ah28 vcc ah29 vpump ah30 gnd aj1 gnd aj2 gnd aj3 gea2/io233ppb5v4 aj4 vcc aj5 io217npb5v2 aj6 vcc aj7 io215npb5v2 aj8 io213ndb5v2 fg896 pin number a3pe3000l function aj9 io213pdb5v2 aj10 io209ndb5v1 aj11 io209pdb5v1 aj12 io203ndb5v1 aj13 io203pdb5v1 aj14 io197ndb5v0 aj15 io195pdb5v0 aj16 io183ndb4v3 aj17 io183pdb4v3 aj18 io179npb4v3 aj19 io177pdb4v2 aj20 io173ndb4v2 aj21 io173pdb4v2 aj22 io163ndb4v1 aj23 io163pdb4v1 aj24 io167npb4v1 aj25 vcc aj26 io156npb4v0 aj27 vcc aj28 tms aj29 gnd aj30 gnd ak2 gnd ak3 gnd ak4 io217ppb5v2 ak5 gnd ak6 io215ppb5v2 ak7 gnd ak8 io207ndb5v1 ak9 io207pdb5v1 ak10 io201ndb5v0 ak11 io201pdb5v0 ak12 io193ndb4v4 ak13 io193pdb4v4 ak14 io197pdb5v0 fg896 pin number a3pe3000l function
package pin assignments 4-54 revision 13 ak15 io191ndb4v4 ak16 io191pdb4v4 ak17 io189ndb4v4 ak18 io189pdb4v4 ak19 io179ppb4v3 ak20 io175ndb4v2 ak21 io175pdb4v2 ak22 io169ndb4v1 ak23 io169pdb4v1 ak24 gnd ak25 io167ppb4v1 ak26 gnd ak27 gdc2/io156ppb4v0 ak28 gnd ak29 gnd b1 gnd b2 gnd b3 gaa2/io309ppb7v4 b4 vcc b5 io14ppb0v1 b6 vcc b7 io07ppb0v0 b8 io09pdb0v1 b9 io15ppb0v1 b10 io19ndb0v2 b11 io19pdb0v2 b12 io29ndb0v3 b13 io29pdb0v3 b14 io31ppb0v3 b15 io37ndb0v4 b16 io37pdb0v4 b17 io41pdb1v0 b18 io51ndb1v1 b19 io59pdb1v2 b20 io53pdb1v1 fg896 pin number a3pe3000l function b21 io53ndb1v1 b22 io61ndb1v2 b23 io61pdb1v2 b24 io69npb1v3 b25 vcc b26 gbc0/io79npb1v4 b27 vcc b28 io64npb1v2 b29 gnd b30 gnd c1 gnd c2 io309npb7v4 c3 vcc c4 gaa0/io00npb0v0 c5 vccib0 c6 io03pdb0v0 c7 io03ndb0v0 c8 gab1/io01pdb0v0 c9 io05pdb0v0 c10 io15npb0v1 c11 io25ndb0v3 c12 io25pdb0v3 c13 io31npb0v3 c14 io27ndb0v3 c15 io39ndb0v4 c16 io39pdb0v4 c17 io55ppb1v1 c18 io51pdb1v1 c19 io59ndb1v2 c20 io63ndb1v2 c21 io63pdb1v2 c22 io67ndb1v3 c23 io67pdb1v3 c24 io75ndb1v4 c25 io75pdb1v4 fg896 pin number a3pe3000l function c26 vccib1 c27 io64ppb1v2 c28 vcc c29 gba1/io81ppb1v4 c30 gnd d1 io303ppb7v3 d2 vcc d3 io305npb7v3 d4 gnd d5 gaa1/io00ppb0v0 d6 gac1/io02pdb0v0 d7 io06npb0v0 d8 gab0/io01ndb0v0 d9 io05ndb0v0 d10 io11ndb0v1 d11 io11pdb0v1 d12 io23ndb0v2 d13 io23pdb0v2 d14 io27pdb0v3 d15 io40pdb0v4 d16 io47ndb1v0 d17 io47pdb1v0 d18 io55npb1v1 d19 io65ndb1v3 d20 io65pdb1v3 d21 io71ndb1v3 d22 io71pdb1v3 d23 io73ndb1v4 d24 io73pdb1v4 d25 io74ndb1v4 d26 gbb0/io80npb1v4 d27 gnd d28 gba0/io81npb1v4 d29 vcc d30 gba2/io82ppb2v0 fg896 pin number a3pe3000l function
proasic3l low power flash fpgas revision 13 4-55 e1 gnd e2 io303npb7v3 e3 vccib7 e4 io305ppb7v3 e5 vcc e6 gac0/io02ndb0v0 e7 vccib0 e8 io06ppb0v0 e9 io24ndb0v2 e10 io24pdb0v2 e11 io13ndb0v1 e12 io13pdb0v1 e13 io34ndb0v4 e14 io34pdb0v4 e15 io40ndb0v4 e16 io49ndb1v1 e17 io49pdb1v1 e18 io50pdb1v1 e19 io58pdb1v2 e20 io60ndb1v2 e21 io77pdb1v4 e22 io68ndb1v3 e23 io68pdb1v3 e24 vccib1 e25 io74pdb1v4 e26 vcc e27 gbb1/io80ppb1v4 e28 vccib2 e29 io82npb2v0 e30 gnd f1 io296ppb7v2 f2 vcc f3 io306pdb7v4 f4 io297pdb7v2 f5 vmv7 fg896 pin number a3pe3000l function f5 vmv7 f6 gnd f7 gndq f8 io12ndb0v1 f9 io12pdb0v1 f10 io10pdb0v1 f11 io16pdb0v1 f12 io22ndb0v2 f13 io30ndb0v3 f14 io30pdb0v3 f15 io36pdb0v4 f16 io48ndb1v0 f17 io48pdb1v0 f18 io50ndb1v1 f19 io58ndb1v2 f20 io60pdb1v2 f21 io77ndb1v4 f22 io72ndb1v3 f23 io72pdb1v3 f24 gndq f25 gnd f26 vmv2 f26 vmv2 f27 io86pdb2v0 f28 io92pdb2v1 f29 vcc f30 io100npb2v2 g1 gnd g2 io296npb7v2 g3 io306ndb7v4 g4 io297ndb7v2 g5 vccib7 g6 gndq g6 gndq g7 vcc fg896 pin number a3pe3000l function g8 vmv0 g9 vccib0 g10 io10ndb0v1 g11 io16ndb0v1 g12 io22pdb0v2 g13 io26ppb0v3 g14 io38npb0v4 g15 io36ndb0v4 g16 io46ndb1v0 g17 io46pdb1v0 g18 io56ndb1v1 g19 io56pdb1v1 g20 io66ndb1v3 g21 io66pdb1v3 g22 vccib1 g23 vmv1 g24 vcc g25 gndq g25 gndq g26 vccib2 g27 io86ndb2v0 g28 io92ndb2v1 g29 io100ppb2v2 g30 gnd h1 io294pdb7v2 h2 io294ndb7v2 h3 io300ndb7v3 h4 io300pdb7v3 h5 io295pdb7v2 h6 io299pdb7v3 h7 vcompla h8 gnd h9 io08ndb0v0 h10 io08pdb0v0 h11 io18pdb0v2 fg896 pin number a3pe3000l function
package pin assignments 4-56 revision 13 h12 io26npb0v3 h13 io28ndb0v3 h14 io28pdb0v3 h15 io38ppb0v4 h16 io42ndb1v0 h17 io52ndb1v1 h18 io52pdb1v1 h19 io62ndb1v2 h20 io62pdb1v2 h21 io70ndb1v3 h22 io70pdb1v3 h23 gnd h24 vcomplb h25 gbc2/io84pdb2v0 h26 io84ndb2v0 h27 io96pdb2v1 h28 io96ndb2v1 h29 io89pdb2v0 h30 io89ndb2v0 j1 io290ndb7v2 j2 io290pdb7v2 j3 io302ndb7v3 j4 io302pdb7v3 j5 io295ndb7v2 j6 io299ndb7v3 j7 vccib7 j8 vccpla j9 vcc j10 io04npb0v0 j11 io18ndb0v2 j12 io20ndb0v2 j13 io20pdb0v2 j14 io32ndb0v3 j15 io32pdb0v3 j16 io42pdb1v0 fg896 pin number a3pe3000l function j17 io44ndb1v0 j18 io44pdb1v0 j19 io54ndb1v1 j20 io54pdb1v1 j21 io76npb1v4 j22 vcc j23 vccplb j24 vccib2 j25 io90pdb2v1 j26 io90ndb2v1 j27 gbb2/io83pdb2v0 j28 io83ndb2v0 j29 io91pdb2v1 j30 io91ndb2v1 k1 io288ndb7v1 k2 io288pdb7v1 k3 io304ndb7v3 k4 io304pdb7v3 k5 gab2/io308pdb7v4 k6 io308ndb7v4 k7 io301pdb7v3 k8 io301ndb7v3 k9 gac2/io307ppb7v4 k10 vcc k11 io04ppb0v0 k12 vccib0 k13 vccib0 k14 vccib0 k15 vccib0 k16 vccib1 k17 vccib1 k18 vccib1 k19 vccib1 k20 io76ppb1v4 k21 vcc fg896 pin number a3pe3000l function k22 io78ppb1v4 k23 io88ndb2v0 k24 io88pdb2v0 k25 io94pdb2v1 k26 io94ndb2v1 k27 io85pdb2v0 k28 io85ndb2v0 k29 io93pdb2v1 k30 io93ndb2v1 l1 io286ndb7v1 l2 io286pdb7v1 l3 io298ndb7v3 l4 io298pdb7v3 l5 io283pdb7v1 l6 io291ndb7v2 l7 io291pdb7v2 l8 io293pdb7v2 l9 io293ndb7v2 l10 io307npb7v4 l11 vcc l12 vcc l13 vcc l14 vcc l15 vcc l16 vcc l17 vcc l18 vcc l19 vcc l20 vcc l21 io78npb1v4 l22 io104npb2v2 l23 io98ndb2v2 l24 io98pdb2v2 l25 io87pdb2v0 l26 io87ndb2v0 fg896 pin number a3pe3000l function
proasic3l low power flash fpgas revision 13 4-57 l27 io97pdb2v1 l28 io101pdb2v2 l29 io103pdb2v2 l30 io119ndb3v0 m1 io282ndb7v1 m2 io282pdb7v1 m3 io292ndb7v2 m4 io292pdb7v2 m5 io283ndb7v1 m6 io285pdb7v1 m7 io287pdb7v1 m8 io289pdb7v1 m9 io289ndb7v1 m10 vccib7 m11 vcc m12 gnd m13 gnd m14 gnd m15 gnd m16 gnd m17 gnd m18 gnd m19 gnd m20 vcc m21 vccib2 m22 nc m23 io104ppb2v2 m24 io102pdb2v2 m25 io102ndb2v2 m26 io95pdb2v1 m27 io97ndb2v1 m28 io101ndb2v2 m29 io103ndb2v2 m30 io119pdb3v0 n1 io276pdb7v0 fg896 pin number a3pe3000l function n2 io278pdb7v0 n3 io280pdb7v0 n4 io284pdb7v1 n5 io279pdb7v0 n6 io285ndb7v1 n7 io287ndb7v1 n8 io281ndb7v0 n9 io281pdb7v0 n10 vccib7 n11 vcc n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd n17 gnd n18 gnd n19 gnd n20 vcc n21 vccib2 n22 io106ndb2v3 n23 io106pdb2v3 n24 io108pdb2v3 n25 io108ndb2v3 n26 io95ndb2v1 n27 io99ndb2v2 n28 io99pdb2v2 n29 io107pdb2v3 n30 io107ndb2v3 p1 io276ndb7v0 p2 io278ndb7v0 p3 io280ndb7v0 p4 io284ndb7v1 p5 io279ndb7v0 p6 gfc1/io275pdb7v0 fg896 pin number a3pe3000l function p7 gfc0/io275ndb7v0 p8 io277pdb7v0 p9 io277ndb7v0 p10 vccib7 p11 vcc p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p17 gnd p18 gnd p19 gnd p20 vcc p21 vccib2 p22 gcc1/io112pdb2v3 p23 io110pdb2v3 p24 io110ndb2v3 p25 io109ppb2v3 p26 io111npb2v3 p27 io105pdb2v2 p28 io105ndb2v2 p29 gcc2/io117pdb3v0 p30 io117ndb3v0 r1 gfc2/io270pdb6v4 r2 gfb1/io274ppb7v0 r3 vcomplf r4 gfa0/io273ndb6v4 r5 gfb0/io274npb7v0 r6 io271ndb6v4 r7 gfb2/io271pdb6v4 r8 io269pdb6v4 r9 io269ndb6v4 r10 vccib7 r11 vcc fg896 pin number a3pe3000l function
package pin assignments 4-58 revision 13 r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd r17 gnd r18 gnd r19 gnd r20 vcc r21 vccib2 r22 gcc0/io112ndb2v3 r23 gcb2/io116pdb3v0 r24 io118pdb3v0 r25 io111ppb2v3 r26 io122ppb3v1 r27 gca0/io114npb3v0 r28 vcomplc r29 gcb1/io113ppb2v3 r30 io115npb3v0 t1 io270ndb6v4 t2 vccplf t3 gfa2/io272ppb6v4 t4 gfa1/io273pdb6v4 t5 io272npb6v4 t6 io267ndb6v4 t7 io267pdb6v4 t8 io265pdb6v3 t9 io263pdb6v3 t10 vccib6 t11 vcc t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd fg896 pin number a3pe3000l function t17 gnd t18 gnd t19 gnd t20 vcc t21 vccib3 t22 io109npb2v3 t23 io116ndb3v0 t24 io118ndb3v0 t25 io122npb3v1 t26 gca1/io114ppb3v0 t27 gcb0/io113npb2v3 t28 gca2/io115ppb3v0 t29 vccplc t30 io121pdb3v0 u1 io268pdb6v4 u2 io264ndb6v3 u3 io264pdb6v3 u4 io258pdb6v3 u5 io258ndb6v3 u6 io257ppb6v2 u7 io261ppb6v3 u8 io265ndb6v3 u9 io263ndb6v3 u10 vccib6 u11 vcc u12 gnd u13 gnd u14 gnd u15 gnd u16 gnd u17 gnd u18 gnd u19 gnd u20 vcc u21 vccib3 fg896 pin number a3pe3000l function u22 io120pdb3v0 u23 io128pdb3v1 u24 io124pdb3v1 u25 io124ndb3v1 u26 io126pdb3v1 u27 io129pdb3v1 u28 io127pdb3v1 u29 io125pdb3v1 u30 io121ndb3v0 v1 io268ndb6v4 v2 io262pdb6v3 v3 io260pdb6v3 v4 io252pdb6v2 v5 io257npb6v2 v6 io261npb6v3 v7 io255pdb6v2 v8 io259pdb6v3 v9 io259ndb6v3 v10 vccib6 v11 vcc v12 gnd v13 gnd v14 gnd v15 gnd v16 gnd v17 gnd v18 gnd v19 gnd v20 vcc v21 vccib3 v22 io120ndb3v0 v23 io128ndb3v1 v24 io132pdb3v2 v25 io130ppb3v2 v26 io126ndb3v1 fg896 pin number a3pe3000l function
proasic3l low power flash fpgas revision 13 4-59 v27 io129ndb3v1 v28 io127ndb3v1 v29 io125ndb3v1 v30 io123pdb3v1 w1 io266ndb6v4 w2 io262ndb6v3 w3 io260ndb6v3 w4 io252ndb6v2 w5 io251ndb6v2 w6 io251pdb6v2 w7 io255ndb6v2 w8 io249ppb6v1 w9 io253pdb6v2 w10 vccib6 w11 vcc w12 gnd w13 gnd w14 gnd w15 gnd w16 gnd w17 gnd w18 gnd w19 gnd w20 vcc w21 vccib3 w22 io134pdb3v2 w23 io138pdb3v3 w24 io132ndb3v2 w25 io136npb3v2 w26 io130npb3v2 w27 io141pdb3v3 w28 io135pdb3v2 w29 io131pdb3v2 w30 io123ndb3v1 y1 io266pdb6v4 fg896 pin number a3pe3000l function y2 io250pdb6v2 y3 io250ndb6v2 y4 io246pdb6v1 y5 io247ndb6v1 y6 io247pdb6v1 y7 io249npb6v1 y8 io245pdb6v1 y9 io253ndb6v2 y10 geb0/io235npb6v0 y11 vcc y12 vcc y13 vcc y14 vcc y15 vcc y16 vcc y17 vcc y18 vcc y19 vcc y20 vcc y21 io142ppb3v3 y22 io134ndb3v2 y23 io138ndb3v3 y24 io140ndb3v3 y25 io140pdb3v3 y26 io136ppb3v2 y27 io141ndb3v3 y28 io135ndb3v2 y29 io131ndb3v2 y30 io133pdb3v2 fg896 pin number a3pe3000l function

revision 13 5-1 5 ? datasheet information list of changes the following table lists critical changes that were made in each version of the proasic3l datasheet. revision changes page revision 13 (january 2013) the "proasic3l ordering information" section has been updated to mention "y" as "blank" mentioning "device does not include license to implement ip based on the cryptography research, inc. (cri ) patent portfolio" (sar 43221). 1-iii added following notes to table 2-2 ? recommended operating conditions 1 : "all proasic3l devices must be programmed wit h the vcc core voltage at 1.5 v" (sar 39910) and "the programming temperature range supported is tambient = 0c to 85c" (sar 43645). 2-2 the note in table 2-212 ? proasic3l ccc/pll specification and table 2-213 ? proasic3l ccc/pll specification referring the reader to smartgen was revised to refer instead to the online help associated with the core (sar 42572). 2-132 , 2-133 signal names have been made consistent (sar 38910). na libero integrated design environment (i de) was changed to libero system-on-chip (soc) throughout the document (sar 40286). live at power-up (lapu) has been replaced with ?instant on?. na revision 12 (september 2012) the "security" section was modified to clarify that microsemi does not support read- back of programmed data. 1-2 revision 11 (august 2012) added a note stating " vmv pins must be connected to the corresponding vcci pins. see the "vmvx i/o supply voltage (quiet)" section on page 3-1 for further information." to table 2-1 ? absolute maximum ratings and table 2-2 ? recommended operating conditions 1 (sar 38316). 2-1 2-2 the "quiescent supply current" section was updated. table 2-7 ? power supply state per mode is new, and table 2-9 ? quiescent supply current (idd) characteristics, proasic3l sleep mode* and table 2-11 ? quiescent supply current (idd) characteristics, no flash*freeze mode1 were updated for core voltage 1.2 v. notes were also updated for table 2-9 , ta b l e 2 - 1 0 , and ta b l e 2 - 11 (sar 34746). 2-7 2-8 the drive strength, iol, and ioh value fo r 3.3 v gtl and 2.5 v gtl was changed from 25 ma to 20 ma in the following tables (sar 37364): table 2-23 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings table 2-29 ? summary of i/o timing characteristics?software default settings table 2-32 ? summary of i/o timing characteristics?software default settings table 2-36 ? i/o output buffer maximum resistances1 table 2-40 ? i/o short currents iosh/iosl table 2-134 ? minimum and maximum dc input and output levels table 2-138 ? minimum and maximum dc input and output levels also added note stating "output drive strength is below jede c specification." for tables table 2-29 , ta b l e 2 - 3 2 , ta b l e 2 - 3 6 , and ta b l e 2 - 4 0 . additionally, the iol and ioh values for 3.3 v gtl+ and 2.5 v gtl+ were corrected from 51 to 35 (for 3.3 v gtl+) and from 40 to 33 (for 2.5 v gtl+) in table ta b l e 2 - 2 3 (sar 39715). 2-22 2-27 2-30 2-34 2-38 2-83 2-85
datasheet information 5-2 revision 13 revision 11 continued figure 2-12 ? ac loading in the "3.3 v pci, 3.3 v pci-x" section was updated to match table 2-127 ? ac waveforms, measuring points, and capacitive loads (sar 34890). 2-81 in table 2-180 ? minimum and maximum dc input and output levels , vil and vih were revised so that the maximum is 3.6 v for all listed values of vcci (sar 37690). 2-103 the following sentence was removed from the "vmvx i/o supply voltage (quiet)" section in the "pin descriptions and packaging" chapter: "within the package, the vmv plane is decoupled from the simultaneous s witching noise originating from the output buffer vcci domain" and replaced with ?wit hin the package, the vmv plane biases the input stage of the i/os in the i/o banks? (sar 38316). the datasheet mentions that "vmv pins must be connected to t he corresponding vcci pins" for an esd enhancement. 3-1 pin k15 of the "fg484" pin table for a3p600l was corrected from vvb1 to vccib1 (sar 38788). 4-35 revision 10 (may 2012) the "in-system programming (isp) and security" section and "security" section were revised to clarify that although no existi ng security measures can give an absolute guarantee, microsemi fpgas im plement the best security available in the industry (sar 34670). i , 1-2 the y security option and licensed dpa logo were added to the "proasic3l ordering information" section . the trademarked licensed dpa logo identifies that a product is covered by a dpa counter-measures licen se from cryptography research (sar 34728). iii the "proasic3l device status" table was updated to show that all proasic3l devices have changed in status from advance to production (sar 38198). iv the opening sentence of the "general description" section was revised for clarity to "the proasic3l family of microsemi flash fpgas dramatically reduces dynamic power consumption by 40% and static power by 50% compared to the equivalent proasic3 device" (sar 22661). 1-1 the following sentence was removed from the "advanced architecture" section : "in addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 v) programming of proasic3l devices via an ieee 1532 jt ag interface" (sar 34690). 1-3 the "specifying i/o states du ring programming" section is new (sar 34700). 1-8 table 1-1 ? i/o standards supported is new. the "i/os with advanced i/o standards" section was revised to add definitions of hot-swap and cold-sparing (sar 37732). 1-7 in table 2-2 ? recommended operating conditions 1 , vpump programming voltage for operation was changed from "0 to 3.45 v" to "0 to 3.6 v" (sar 32257). 2-2 values for 1.5 v were added to table 2-8 ? quiescent supply current (idd) characteristics, proasic3l flash*freeze mode* and table 2-11 ? quiescent supply current (idd) characteristics, no flash*freeze mode1 (sar 30578). 2-7 , 2-8 the reference to guidelines for global spines and versatile rows, given in the "global clock contribution?pclock" section , was corrected to t he "spine architecture" section of the global re sources chapter in the proasic3l fpga fabric user's guide (sar 34737). 2-15 t dout was corrected to t din in figure 2-4 ? input buffer timing model and delays (example) (sar 37110). 2-19 revision changes page
proasic3l low power flash fpgas revision 13 5-3 revision 10 continued 3.3 v lvcmos and 1.2 v lvcmos wide range were added to applicable tables in the "overview of i/o pe rformance" section and "detailed i/o dc charac teristics" section . values for 1.2 v lvcmos were added to tables in the "detailed i/o dc characteristics" section . the "3.3 v lvcmos wide range" section and "1.2 v lvcmos wide range" section , with minimum and maximum dc input and output levels tables, are new. complete timing data for wide range will be available in a later revision of the datasheet (sars 37161, 38188). 2-22 , 2-33 , 2-50 , 2-80 the notes regarding drive strength in the "summary of i/o timing characteristics ? default i/o software settings" section tables were revised for clarification. they now state that the minimum drive strength for t he default software configuration when run in wide range is 100 a. the drive strength displayed in software is supported in normal range only. for a detailed i/v curve, refer to the ibis models (sar 34761). 2-26 table 2-39 ? i/o weak pull-up/pull-down resistances was updated with additional values and the definitions of r weak pull-up-max and r weak pull-down-max were corrected (sar 34756). 2-37 the paragraph above table 2-44 ? duration of short circuit event before failure was revised to change the maximum temperature from 110c to 100c, with an example of six months instead of three months. the row for 110c was removed from the table for consistency with table 2-2 ? recommended operating conditions 1 (sar 34744). 2-41 the ac loading figures in the "single-ended i/o characteristics" section were updated to match tables in the "summary of i/o timing characteristics ? default i/o software settings" section (sar 34890). 2-42 , 2-26 the following sentence was deleted from the "2.5 v lvcmos" section (sar 34797): "it uses a 5 v?tolerant input buffe r and push-pull output buffer." 2-52 the table notes were revised for lvds table 2-174 ? minimum and maximum dc input and output levels (sar 34813). 2-100 values for the maximum frequency for input and output ddr were added to tables in the "ddr module specifications" section (sar 34805). 2-115 minimum pulse width high and low values were added to the tables in the "global tree timing characteristics" section . the maximum frequency for global clock parameter was removed from these tables because a frequency on the global is only an indication of what the global network c an do. there are other limiters such as the sram, i/os, and pll. smarttime software should be used to determine the design frequency (sar 36965). 2-128 table 2-212 ? proasic3l ccc/pll specification and table 2-212 ? proasic3l ccc/pll specification were updated. a note was added to indicate that when the ccc/pll core is generated by microsemi core generator software, not all delay values of the specified delay increments are available (sar 34825). 2-132 , 2-133 figure 2-46 ? write access after write onto same address, figure 2-47 ? read access after write onto same address , and figure 2-48 ? write access after read onto same address were deleted. reference was made to a new application note, simultaneous read-write operations in dual-port sram for flash-based csocs and fpga s , which covers these cases in detail (sar 34873). the port names in the sram "timing waveforms" , sram "timing characteristics" tables, figure 2-50 ? fifo reset , and the fifo "timing characteristics" tables were revised to ensure consistency with the software names (sar 35751). 2-135 , 2-138 , 2-144 , 2-146 figure 2-48 ? fifo read and figure 2-49 ? fifo write are new (sar 34849). 2-143 the "pin descriptions and packaging" chapter is new (sar 34773). 3-1 revision changes page
datasheet information 5-4 revision 13 revision 10 (continued) package names used in the "package pin assignments" section were revised to match standards given in package mechanical drawings (sar 34773). 4-1 july 2010 the versioning system for datasheets has been changed. datasheets are assigned a revision number that increments each time the datasheet is revised. the "proasic3l device status" table on page iv indicates the status for each device in the device family. n/a revision changes page
proasic3l low power flash fpgas revision 13 5-5 revision changes page revision 9 (feb 2009) product brief v1.3 the "i/os per package 1" table was revised to change the number of differential i/o pairs for a3pe3000l from 300 to 310. ii table 2 ? proasic3l fpgas package sizes dimensions is new. ii revision 8 (feb 2009) product brief v1.2 the "advanced and pro (professional) i/os" section was revised to add two bullets regarding wide range power supply voltage support. i 3.0 v wide range was added to the list of supported voltages in the "i/os with advanced i/o standards" section . the "wide range i/o support" section is new. 1-7 revision 7 (aug 2008) dc and switching characteristics advance v0.6 3.0 v lvcmos wide range support data was added to table 2-2 ? recommended operating conditions 1 . 2-2 3.3 v lvcmos wide range support data was added to table 2-23 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings to table 2-25 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings . 2-22 to 2-24 3.3 v lvcmos wide range support data was added to table 2-27 ? summary of ac measuring points . 2-26 3.3 v lvcmos wide range support text was added to the "3.3 v lvttl / 3.3 v lvcmos" section . 2-42 table 2-62 ? minimum and maximum dc input and output levels for lvcmos 3.3 v wide range is new. 2-50 revision 6 (aug 2008) dc and switching characteristics advance v0.5 table 2-6 ? temperature and voltage derating factors for timing delays was updated to add several new rows of values. 2-7 table 2-8 ? quiescent supply current (idd) characteristics, proasic3l flash*freeze mode* through table 2-11 ? quiescent supply current (idd) characteristics, no flash*freeze mode1 were updated to add 1.5 v core voltage. 2-7 to 2-8 table 2-19 ? different components contributing to dynamic power consumption in proasic3l devices at 1.5 v vcc is new. 2-14 table 2-20 ? different components contribut ing to the static power consumption in proasic3l devices was updated to add the static pll contribution at 1.5 v core operation. 2-14 timing tables were updated to include tables for 1.5 v core voltage. n/a table 2-212 ? proasic3l ccc/pll specification was updated for core voltage 1.2 v and table 2-213 ? proasic3l ccc/pll specification for 1.5 v is new. 2-132 , 2-133 revision 5 (jul 2008) product brief v1.1 dc and switching characteristics advance v0.4 as a result of the libero ide v8.4 rel ease, actel now offers a wide range of core voltage support. the document was u pdated to change 1.2 v / 1.5 v to 1.2 v to 1.5 v. n/a
datasheet information 5-6 revision 13 revision 4 (june 2008) dc and switching characteristics advance v0.3 tables have been updated to include the lvcmos 1.2 v i/o set. ddr tables have two additional data points added to reflect both edges for input ddr setup and hold time. power data table has been updated to match smartpower data rather then simulation values. n/a table 2-1 ? absolute maximum ratings was updated to add vmv to the vcci parameter row and to remove the word "o utput" from the parameter description for vcci. table note 3 was added. 2-1 table 2-2 ? recommended operating conditions 1 was updated to add table note references and rearrange the order of notes. vmv was added to the vcci parameter row. a new row was added for vcc, 1.5 v dc core supply voltage. the table note stating that 1.5 v data will be released at a later date is new. the table note on vmv pins is new. 2-2 table 2-4 ? overshoot and undershoot limits 1 . the title was revised to remove "as measured on quiet i/os." table note 2 was revised to remove "estimated sso density over cycles." table note 3 wa s revised to remove "refers only to overshoot/undershoot limits for simultaneous switching i/os. " 2-3 eq 2 was updated. the temperature was changed to 100c, and therefore the end result changed. 2-6 the table notes for table 2-8 ? quiescent supply current (idd) characteristics, proasic3l flash*freeze mode* and table 2-9 ? quiescent supply current (idd) characteristics, proasic3l sleep mode* were updated to remove vmv and include p dc6 and p dc7 . the table note for table 2-8 ? quiescent supply current (idd) characteristics, proasic3l flash*freeze mode* was updated to include vjtag. 2-7 table 2-10 ? quiescent supply current (idd) characteristics, shutdown mode is new. 2-8 note 2 of table 2-11 ? quiescent supply current (idd) characteristics, no flash*freeze mode1 was updated to include vccpll. note 4 was updated to include pdc6 and pdc7. 2-8 table 2-12 ? summary of i/o input buffer power (per pin) ? default i/o software settings through table 2-17 ? summary of i/o outp ut buffer power (per pin) ? default i/o software settings 1 were updated to change pdc2 to pdc6 and pdc3 to pdc7. the table notes were updated to reflect that power was measured on vcci. the subtitle of the table was changed from "applicable to advanced i/o banks" to "applicable to pro i/o banks." 2-9 through 2-12 the word "input" in the titles of table 2-15 ? summary of i/o output buffer power (per pin) ? default i/o software settings 1 and table 2-16 ? summary of i/o output buffer power (per pin) ? default i/o software settings 1 , was changed to "output." 2-11 , 2-12 the value of c load for single-ended 3.3 v pci was changed to 10 from 5 in table 2-15 ? summary of i/o output buffer power (per pin) ? default i/o software settings 1 through table 2-17 ? summary of i/o output buffer power (per pin) ? default i/o software settings 1 . 2-11 through 2-12 revision changes page
proasic3l low power flash fpgas revision 13 5-7 revision 4 (cont?d) the last section of table 2-18 ? different components contributing to dynamic power consumption in proasic3l devices at 1.2 v vcc was made into a new table: table 2-19 ? different components contributing to dynamic power consumption in proasic3l devices at 1.5 v vcc . the table numbers referenced for device-specific dynamic power for p ac9 and p ac10 were changed in table 2-18 ? different components contributing to dynamic power consumption in proasic3l devices at 1.2 v vcc . the definition of p dc5 was updated and parameters p dc6 and p dc7 were added to table 2-20 ? different components contributing to the static power consumption in proasic3l devices . 2-13 the "total static power consumption?pstat" section was updated to revise the calculation of p stat , including p dc6 and p dc7 . 2-15 footnote 1 was updated to include information about p ac13 . 2-16 table 2-43 ? schmitt trigger input hysteres is, hysteresis voltage value (typ) for schmitt mode input buffers was updated to include the hysteresis value for 1.2 v lvcmos. 2-40 the "1.2 v lvcmos (jesd8-12a)" section is new. 2-76 revision 3 (apri2008) product brief v1.0 the product brief was divided into two sections and given a version number, starting at v1.0. the first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. the second section is a device family overview. n/a packaging v1.1 the "FG324" package diagram was replaced. 4-29 revision 2 (apr 2008) product brief rev. 1 reference to m1a3p250l was removed from table 1 ? proasic3 low-power product family , the "i/os per package 1" table, the "proasic3l ordering information" section , and the "temperature grade offerings" table. the table note regarding m1a3p250l was removed from the "i/os per package 1" table. i , ii , iii , iv revision 1 (feb 2008) the "pll behavior at brownout condition" section is new. 2-4 dc and switching characteristics advance v0.2 table 2-204 ? a3p250l global resource ? applies to 1.5 v dc core voltage , table 2-206 ? a3p600l global resource ? applies to 1.5 v dc core voltage , table 2-208 ? a3p1000l global resource ? applies to 1.5 v dc core voltage , and table 2-210 ? a3pe3000l global resource ? applies to 1.5 v dc core voltage were updated with values for t rckl , t rckh , and t rcksw . 2-128 ? 2-131 the worst-case commercial conditions were added to table 2-221 ? embedded flashrom access time? applies to 1.2 v dc core voltage . 2-148 table 2-18 ? different components contributing to dynamic power consumption in proasic3l devices at 1.2 v vcc was updated to revise the value for p ac14 and add parameters p dc1 through p dc5 to the table. 2-13 revision changes page
datasheet information 5-8 revision 13 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device, as highlighted in the "proasic3l device status" table on page iv , is designated as either "product brief," "advance," "preliminary," or "production." the definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. production this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. safety critical, life support, and high-reliability applications policy the products described in this advance status document may not have completed the microsemi qualification process. products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult the microsemi soc products group terms and conditions for specific liability exclusions relating to life-support applications. a reliability report covering all of the soc products group?s products is available at http://www.microsemi.com/s oc/documents/ort_report.pdf . microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local sales office for additional reliability information.

51700100-13/01.13 ? 2012 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. products incl ude high-performance, high-reliability analog and rf devices, mixed signal and rf integrated circuits, customizable socs, fpgas, and complete subsystems. microsemi is headquarter ed in aliso viejo, calif. learn more at www.microsemi.com . microsemi corporate headquarters one enterprise, aliso viejo ca 92656 usa within the usa: +1 (949) 380-6100 sales: +1 (949) 380-6136 fax: +1 (949) 215-4996

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